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drm/radeon/kms: fix internal tmds setup on legacy display engine
- crtc 0 routing was wrong - need to clear various timing bits in FP_GEN_CNTL - need to set FP_H/V2_SYNC_STRT_WID regs for crtc 1 Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -668,6 +668,9 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod
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WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);
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WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
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WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid);
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WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid);
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} else {
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uint32_t crtc_gen_cntl;
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uint32_t crtc_ext_cntl;
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@ -542,6 +542,14 @@ static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
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fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
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fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN |
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RADEON_FP_DFP_SYNC_SEL |
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RADEON_FP_CRT_SYNC_SEL |
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RADEON_FP_CRTC_LOCK_8DOT |
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RADEON_FP_USE_SHADOW_EN |
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RADEON_FP_CRTC_USE_SHADOW_VEND |
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RADEON_FP_CRT_SYNC_ALT);
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if (1) /* FIXME rgbBits == 8 */
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fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */
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else
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@ -555,7 +563,7 @@ static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
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else
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fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
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} else
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fp_gen_cntl |= RADEON_FP_SEL_CRTC1;
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fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2;
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} else {
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if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
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fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
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