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x86/nospec: Simplify alternative_msr_write()
The macro is not type safe and I did look for why that "g" constraint for the asm doesn't work: it's because the asm is more fundamentally wrong. It does movl %[val], %%eax but "val" isn't a 32-bit value, so then gcc will pass it in a register, and generate code like movl %rsi, %eax and gas will complain about a nonsensical 'mov' instruction (it's moving a 64-bit register to a 32-bit one). Passing it through memory will just hide the real bug - gcc still thinks the memory location is 64-bit, but the "movl" will only load the first 32 bits and it all happens to work because x86 is little-endian. Convert it to a type safe inline function with a little trick which hands the feature into the ALTERNATIVE macro. Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@kernel.org>
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@ -241,15 +241,16 @@ static inline void vmexit_fill_RSB(void)
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#endif
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}
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#define alternative_msr_write(_msr, _val, _feature) \
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asm volatile(ALTERNATIVE("", \
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"movl %[msr], %%ecx\n\t" \
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"movl %[val], %%eax\n\t" \
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"movl $0, %%edx\n\t" \
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"wrmsr", \
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_feature) \
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: : [msr] "i" (_msr), [val] "i" (_val) \
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: "eax", "ecx", "edx", "memory")
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static __always_inline
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void alternative_msr_write(unsigned int msr, u64 val, unsigned int feature)
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{
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asm volatile(ALTERNATIVE("", "wrmsr", %c[feature])
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: : "c" (msr),
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"a" (val),
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"d" (val >> 32),
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[feature] "i" (feature)
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: "memory");
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}
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static inline void indirect_branch_prediction_barrier(void)
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{
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