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ACPI: CPPC: Amend documentation in the comments
Currently it's too hard to read the _CPC structure as it's commented. Reshuffle indentation and style to make it readable. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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@ -604,47 +604,30 @@ static bool is_cppc_supported(int revision, int num_ent)
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/*
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* An example CPC table looks like the following.
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*
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* Name(_CPC, Package()
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* {
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* 17,
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* NumEntries
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* 1,
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* // Revision
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* ResourceTemplate(){Register(PCC, 32, 0, 0x120, 2)},
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* // Highest Performance
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* ResourceTemplate(){Register(PCC, 32, 0, 0x124, 2)},
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* // Nominal Performance
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* ResourceTemplate(){Register(PCC, 32, 0, 0x128, 2)},
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* // Lowest Nonlinear Performance
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* ResourceTemplate(){Register(PCC, 32, 0, 0x12C, 2)},
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* // Lowest Performance
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* ResourceTemplate(){Register(PCC, 32, 0, 0x130, 2)},
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* // Guaranteed Performance Register
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* ResourceTemplate(){Register(PCC, 32, 0, 0x110, 2)},
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* // Desired Performance Register
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* ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)},
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* ..
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* ..
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* ..
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*
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* }
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* Name (_CPC, Package() {
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* 17, // NumEntries
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* 1, // Revision
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* ResourceTemplate() {Register(PCC, 32, 0, 0x120, 2)}, // Highest Performance
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* ResourceTemplate() {Register(PCC, 32, 0, 0x124, 2)}, // Nominal Performance
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* ResourceTemplate() {Register(PCC, 32, 0, 0x128, 2)}, // Lowest Nonlinear Performance
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* ResourceTemplate() {Register(PCC, 32, 0, 0x12C, 2)}, // Lowest Performance
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* ResourceTemplate() {Register(PCC, 32, 0, 0x130, 2)}, // Guaranteed Performance Register
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* ResourceTemplate() {Register(PCC, 32, 0, 0x110, 2)}, // Desired Performance Register
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* ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)},
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* ...
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* ...
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* ...
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* }
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* Each Register() encodes how to access that specific register.
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* e.g. a sample PCC entry has the following encoding:
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*
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* Register (
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* PCC,
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* AddressSpaceKeyword
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* 8,
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* //RegisterBitWidth
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* 8,
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* //RegisterBitOffset
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* 0x30,
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* //RegisterAddress
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* 9
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* //AccessSize (subspace ID)
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* 0
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* )
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* }
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* Register (
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* PCC, // AddressSpaceKeyword
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* 8, // RegisterBitWidth
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* 8, // RegisterBitOffset
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* 0x30, // RegisterAddress
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* 9, // AccessSize (subspace ID)
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* )
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*/
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#ifndef init_freq_invariance_cppc
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