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ASoC: codecs: rx-macro: handle swr_reset correctly

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Reset soundwire block on frame sync generation clock reset.
Without this we are hitting read/write timeouts randomly during
runtime pm. Along with this remove a swr_reset redundant flag.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20220906170112.1984-3-srinivas.kandagatla@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Srinivas Kandagatla 2022-09-06 18:01:02 +01:00 committed by Mark Brown
parent fdc972d4a7
commit 1a4e73915a
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
1 changed files with 5 additions and 11 deletions
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16
sound/soc/codecs/lpass-rx-macro.c
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@ -596,7 +596,6 @@ struct rx_macro {
int rx_port_value[RX_MACRO_PORTS_MAX];
u16 prim_int_users[INTERP_MAX];
int rx_mclk_users;
bool reset_swr;
int clsh_users;
int rx_mclk_cnt;
bool is_ear_mode_on;
@ -3442,18 +3441,15 @@ static int swclk_gate_enable(struct clk_hw *hw)
}
rx_macro_mclk_enable(rx, true);
if (rx->reset_swr)
regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL,
CDC_RX_SWR_RESET_MASK,
CDC_RX_SWR_RESET);
regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL,
CDC_RX_SWR_RESET_MASK,
CDC_RX_SWR_RESET);
regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL,
CDC_RX_SWR_CLK_EN_MASK, 1);
if (rx->reset_swr)
regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL,
CDC_RX_SWR_RESET_MASK, 0);
rx->reset_swr = false;
regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL,
CDC_RX_SWR_RESET_MASK, 0);
return 0;
}
@ -3579,7 +3575,6 @@ static int rx_macro_probe(struct platform_device *pdev)
dev_set_drvdata(dev, rx);
rx->reset_swr = true;
rx->dev = dev;
/* set MCLK and NPL rates */
@ -3701,7 +3696,6 @@ static int __maybe_unused rx_macro_runtime_resume(struct device *dev)
}
regcache_cache_only(rx->regmap, false);
regcache_sync(rx->regmap);
rx->reset_swr = true;
return 0;
err_fsgen: