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riscv: sifive: Add SiFive alternative ports
Add required ports of the Alternative scheme for SiFive. Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
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@ -9,4 +9,14 @@ config RISCV_ERRATA_ALTERNATIVE
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code patching is performed once in the boot stages. It means
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that the overhead from this mechanism is just taken once.
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config ERRATA_SIFIVE
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bool "SiFive errata"
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depends on RISCV_ERRATA_ALTERNATIVE
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help
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All SiFive errata Kconfig depend on this Kconfig. Disabling
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this Kconfig will disable all SiFive errata. Please say "Y"
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here if your platform uses SiFive CPU cores.
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Otherwise, please say "N" here to avoid unnecessary overhead.
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endmenu
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@ -7,6 +7,7 @@ config SOC_SIFIVE
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select CLK_SIFIVE
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select CLK_SIFIVE_PRCI
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select SIFIVE_PLIC
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select ERRATA_SIFIVE
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help
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This enables support for SiFive SoC platform hardware.
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@ -1 +1,2 @@
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obj-y += alternative.o
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obj-$(CONFIG_ERRATA_SIFIVE) += sifive/
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@ -42,6 +42,11 @@ static void __init init_alternative(void)
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riscv_fill_cpu_mfr_info();
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switch (cpu_mfr_info.vendor_id) {
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#ifdef CONFIG_ERRATA_SIFIVE
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case SIFIVE_VENDOR_ID:
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vendor_patch_func = sifive_errata_patch_func;
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break;
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#endif
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default:
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vendor_patch_func = NULL;
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}
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1
arch/riscv/errata/sifive/Makefile
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1
arch/riscv/errata/sifive/Makefile
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@ -0,0 +1 @@
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obj-y += errata.o
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68
arch/riscv/errata/sifive/errata.c
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68
arch/riscv/errata/sifive/errata.c
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@ -0,0 +1,68 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2021 Sifive.
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*/
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/bug.h>
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#include <asm/patch.h>
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#include <asm/alternative.h>
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#include <asm/vendorid_list.h>
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#include <asm/errata_list.h>
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struct errata_info_t {
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char name[ERRATA_STRING_LENGTH_MAX];
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bool (*check_func)(unsigned long arch_id, unsigned long impid);
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};
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static u32 __init sifive_errata_probe(unsigned long archid, unsigned long impid)
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{
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int idx;
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u32 cpu_req_errata = 0;
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for (idx = 0; idx < ERRATA_SIFIVE_NUMBER; idx++)
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if (errata_list[idx].check_func(archid, impid))
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cpu_req_errata |= (1U << idx);
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return cpu_req_errata;
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}
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static void __init warn_miss_errata(u32 miss_errata)
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{
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int i;
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pr_warn("----------------------------------------------------------------\n");
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pr_warn("WARNING: Missing the following errata may cause potential issues\n");
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for (i = 0; i < ERRATA_SIFIVE_NUMBER; i++)
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if (miss_errata & 0x1 << i)
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pr_warn("\tSiFive Errata[%d]:%s\n", i, errata_list[i].name);
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pr_warn("Please enable the corresponding Kconfig to apply them\n");
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pr_warn("----------------------------------------------------------------\n");
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}
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void __init sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
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unsigned long archid, unsigned long impid)
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{
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struct alt_entry *alt;
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u32 cpu_req_errata = sifive_errata_probe(archid, impid);
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u32 cpu_apply_errata = 0;
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u32 tmp;
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for (alt = begin; alt < end; alt++) {
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if (alt->vendor_id != SIFIVE_VENDOR_ID)
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continue;
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if (alt->errata_id >= ERRATA_SIFIVE_NUMBER) {
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WARN(1, "This errata id:%d is not in kernel errata list", alt->errata_id);
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continue;
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}
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tmp = (1U << alt->errata_id);
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if (cpu_req_errata & tmp) {
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patch_text_nosync(alt->old_ptr, alt->alt_ptr, alt->alt_len);
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cpu_apply_errata |= tmp;
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}
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}
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if (cpu_apply_errata != cpu_req_errata)
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warn_miss_errata(cpu_req_errata - cpu_apply_errata);
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}
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@ -32,5 +32,8 @@ struct errata_checkfunc_id {
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bool (*func)(struct alt_entry *alt);
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};
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void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
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unsigned long archid, unsigned long impid);
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#endif
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#endif
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