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perf vendor events intel: Update SkylakeX events to v1.12
Signed-off-by: Andi Kleen <ak@linux.intel.com> Cc: Kan Liang <kan.liang@intel.com> Cc: Jiri Olsa <jolsa@kernel.org> Link: https://lkml.kernel.org/r/20190315165219.GA21223@tassilo.jf.intel.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Andi Kleen
Arnaldo Carvalho de Melo
parent
24339348b9
commit
19f2d40c57
File diff suppressed because it is too large
Load Diff
@ -59,7 +59,6 @@
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"BriefDescription": "Number of Packed Double-Precision FP arithmetic instructions (Use operation multiplier of 8)",
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"Counter": "0,1,2,3",
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"EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE",
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"PublicDescription": "Number of Packed Double-Precision FP arithmetic instructions (Use operation multiplier of 8).",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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@ -69,7 +68,6 @@
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"BriefDescription": "Number of Packed Single-Precision FP arithmetic instructions (Use operation multiplier of 16)",
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"Counter": "0,1,2,3",
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"EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE",
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"PublicDescription": "Number of Packed Single-Precision FP arithmetic instructions (Use operation multiplier of 16).",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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@ -1,14 +1,4 @@
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[
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{
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"EventCode": "0x79",
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"UMask": "0x4",
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"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
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"Counter": "0,1,2,3",
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"EventName": "IDQ.MITE_UOPS",
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"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x79",
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"UMask": "0x4",
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@ -22,11 +12,11 @@
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},
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{
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"EventCode": "0x79",
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"UMask": "0x8",
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"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
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"UMask": "0x4",
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"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
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"Counter": "0,1,2,3",
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"EventName": "IDQ.DSB_UOPS",
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"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ.",
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"EventName": "IDQ.MITE_UOPS",
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"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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@ -41,6 +31,16 @@
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x79",
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"UMask": "0x8",
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"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
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"Counter": "0,1,2,3",
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"EventName": "IDQ.DSB_UOPS",
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"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ.",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x79",
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"UMask": "0x10",
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@ -55,22 +55,22 @@
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{
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"EventCode": "0x79",
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"UMask": "0x18",
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"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
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"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
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"Counter": "0,1,2,3",
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"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
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"CounterMask": "4",
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"PublicDescription": "Counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ.",
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"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
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"CounterMask": "1",
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"PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ.",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x79",
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"UMask": "0x18",
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"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
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"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
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"Counter": "0,1,2,3",
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"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
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"CounterMask": "1",
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"PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ.",
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"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
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"CounterMask": "4",
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"PublicDescription": "Counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ.",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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@ -87,22 +87,22 @@
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{
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"EventCode": "0x79",
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"UMask": "0x24",
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"BriefDescription": "Cycles MITE is delivering 4 Uops",
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"BriefDescription": "Cycles MITE is delivering any Uop",
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"Counter": "0,1,2,3",
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"EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
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"CounterMask": "4",
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"PublicDescription": "Counts the number of cycles 4 uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. Counting includes uops that may 'bypass' the IDQ. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
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"EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
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"CounterMask": "1",
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"PublicDescription": "Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. Counting includes uops that may 'bypass' the IDQ. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x79",
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"UMask": "0x24",
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"BriefDescription": "Cycles MITE is delivering any Uop",
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"BriefDescription": "Cycles MITE is delivering 4 Uops",
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"Counter": "0,1,2,3",
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"EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
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"CounterMask": "1",
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"PublicDescription": "Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. Counting includes uops that may 'bypass' the IDQ. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
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"EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
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"CounterMask": "4",
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"PublicDescription": "Counts the number of cycles 4 uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. Counting includes uops that may 'bypass' the IDQ. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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@ -117,6 +117,16 @@
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x79",
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"UMask": "0x30",
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"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
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"Counter": "0,1,2,3",
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"EventName": "IDQ.MS_UOPS",
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"PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS.",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EdgeDetect": "1",
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"EventCode": "0x79",
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@ -129,16 +139,6 @@
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x79",
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"UMask": "0x30",
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"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
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"Counter": "0,1,2,3",
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"EventName": "IDQ.MS_UOPS",
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"PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS.",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x80",
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"UMask": "0x4",
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@ -177,34 +177,24 @@
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"Invert": "1",
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"EventCode": "0x9C",
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"UMask": "0x1",
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"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
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"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
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"Counter": "0,1,2,3",
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"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
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"PublicDescription": "Counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread. b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions). c. Instruction Decode Queue (IDQ) delivers four uops.",
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"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
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"CounterMask": "1",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x9C",
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"UMask": "0x1",
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"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
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"BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
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"Counter": "0,1,2,3",
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"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
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"CounterMask": "4",
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"PublicDescription": "Counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4.",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x9C",
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"UMask": "0x1",
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"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
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"Counter": "0,1,2,3",
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"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
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"CounterMask": "3",
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"PublicDescription": "Counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >= 3.",
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"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
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"CounterMask": "1",
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"PublicDescription": "Cycles with less than 3 uops delivered by the front-end.",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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@ -222,22 +212,32 @@
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{
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"EventCode": "0x9C",
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"UMask": "0x1",
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"BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
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"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
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"Counter": "0,1,2,3",
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"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
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"CounterMask": "1",
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"PublicDescription": "Cycles with less than 3 uops delivered by the front-end.",
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"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
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"CounterMask": "3",
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"PublicDescription": "Counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >= 3.",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"Invert": "1",
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"EventCode": "0x9C",
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"UMask": "0x1",
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"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
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"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
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"Counter": "0,1,2,3",
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"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
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"CounterMask": "1",
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"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
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"CounterMask": "4",
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"PublicDescription": "Counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4.",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0x9C",
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"UMask": "0x1",
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"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
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"Counter": "0,1,2,3",
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"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
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"PublicDescription": "Counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding \u201c4 \u2013 x\u201d when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread. b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions). c. Instruction Decode Queue (IDQ) delivers four uops.",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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@ -247,86 +247,18 @@
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"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
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"Counter": "0,1,2,3",
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"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
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"PublicDescription": "Counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.",
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"PublicDescription": "Counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 0\u20132 cycles.",
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"SampleAfterValue": "2000003",
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"CounterHTOff": "0,1,2,3,4,5,6,7"
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},
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{
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"EventCode": "0xC6",
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"UMask": "0x1",
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"BriefDescription": "Retired Instructions who experienced decode stream buffer (DSB - the decoded instruction-cache) miss. Precise Event.",
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"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall. Precise Event.",
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"PEBS": "1",
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"MSRValue": "0x11",
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"MSRValue": "0x400406",
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"Counter": "0,1,2,3",
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"EventName": "FRONTEND_RETIRED.DSB_MISS",
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"MSRIndex": "0x3F7",
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"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. \r\n",
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"TakenAlone": "1",
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"SampleAfterValue": "100007",
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"CounterHTOff": "0,1,2,3"
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},
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{
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"EventCode": "0xC6",
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"UMask": "0x1",
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"BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss. Precise Event.",
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"PEBS": "1",
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"MSRValue": "0x12",
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"Counter": "0,1,2,3",
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"EventName": "FRONTEND_RETIRED.L1I_MISS",
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"MSRIndex": "0x3F7",
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"TakenAlone": "1",
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"SampleAfterValue": "100007",
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"CounterHTOff": "0,1,2,3"
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},
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{
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"EventCode": "0xC6",
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"UMask": "0x1",
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"BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss. Precise Event.",
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"PEBS": "1",
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"MSRValue": "0x13",
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"Counter": "0,1,2,3",
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"EventName": "FRONTEND_RETIRED.L2_MISS",
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"MSRIndex": "0x3F7",
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"TakenAlone": "1",
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"SampleAfterValue": "100007",
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"CounterHTOff": "0,1,2,3"
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},
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{
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"EventCode": "0xC6",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Retired Instructions who experienced iTLB true miss. Precise Event.",
|
||||
"PEBS": "1",
|
||||
"MSRValue": "0x14",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "FRONTEND_RETIRED.ITLB_MISS",
|
||||
"MSRIndex": "0x3F7",
|
||||
"PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss.",
|
||||
"TakenAlone": "1",
|
||||
"SampleAfterValue": "100007",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC6",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss. Precise Event.",
|
||||
"PEBS": "1",
|
||||
"MSRValue": "0x15",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "FRONTEND_RETIRED.STLB_MISS",
|
||||
"MSRIndex": "0x3F7",
|
||||
"PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss.",
|
||||
"TakenAlone": "1",
|
||||
"SampleAfterValue": "100007",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC6",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall. Precise Event.",
|
||||
"PEBS": "1",
|
||||
"MSRValue": "0x400206",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2",
|
||||
"EventName": "FRONTEND_RETIRED.LATENCY_GE_4",
|
||||
"MSRIndex": "0x3F7",
|
||||
"TakenAlone": "1",
|
||||
"SampleAfterValue": "100007",
|
||||
@ -348,11 +280,11 @@
|
||||
{
|
||||
"EventCode": "0xC6",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall. Precise Event.",
|
||||
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall. Precise Event.",
|
||||
"PEBS": "1",
|
||||
"MSRValue": "0x400406",
|
||||
"MSRValue": "0x400206",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "FRONTEND_RETIRED.LATENCY_GE_4",
|
||||
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2",
|
||||
"MSRIndex": "0x3F7",
|
||||
"TakenAlone": "1",
|
||||
"SampleAfterValue": "100007",
|
||||
@ -361,13 +293,13 @@
|
||||
{
|
||||
"EventCode": "0xC6",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.",
|
||||
"BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss. Precise Event.",
|
||||
"PEBS": "1",
|
||||
"MSRValue": "0x400806",
|
||||
"MSRValue": "0x15",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "FRONTEND_RETIRED.LATENCY_GE_8",
|
||||
"EventName": "FRONTEND_RETIRED.STLB_MISS",
|
||||
"MSRIndex": "0x3F7",
|
||||
"PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops. \r\n",
|
||||
"PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss.",
|
||||
"TakenAlone": "1",
|
||||
"SampleAfterValue": "100007",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
@ -375,13 +307,13 @@
|
||||
{
|
||||
"EventCode": "0xC6",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall. Precise Event.",
|
||||
"BriefDescription": "Retired Instructions who experienced iTLB true miss. Precise Event.",
|
||||
"PEBS": "1",
|
||||
"MSRValue": "0x401006",
|
||||
"MSRValue": "0x14",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "FRONTEND_RETIRED.LATENCY_GE_16",
|
||||
"EventName": "FRONTEND_RETIRED.ITLB_MISS",
|
||||
"MSRIndex": "0x3F7",
|
||||
"PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.\r\n",
|
||||
"PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss.",
|
||||
"TakenAlone": "1",
|
||||
"SampleAfterValue": "100007",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
@ -389,25 +321,11 @@
|
||||
{
|
||||
"EventCode": "0xC6",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall. Precise Event.",
|
||||
"BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss. Precise Event.",
|
||||
"PEBS": "1",
|
||||
"MSRValue": "0x402006",
|
||||
"MSRValue": "0x13",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "FRONTEND_RETIRED.LATENCY_GE_32",
|
||||
"MSRIndex": "0x3F7",
|
||||
"PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.\r\n",
|
||||
"TakenAlone": "1",
|
||||
"SampleAfterValue": "100007",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC6",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall. Precise Event.",
|
||||
"PEBS": "1",
|
||||
"MSRValue": "0x404006",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "FRONTEND_RETIRED.LATENCY_GE_64",
|
||||
"EventName": "FRONTEND_RETIRED.L2_MISS",
|
||||
"MSRIndex": "0x3F7",
|
||||
"TakenAlone": "1",
|
||||
"SampleAfterValue": "100007",
|
||||
@ -416,11 +334,65 @@
|
||||
{
|
||||
"EventCode": "0xC6",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall. Precise Event.",
|
||||
"BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss. Precise Event.",
|
||||
"PEBS": "1",
|
||||
"MSRValue": "0x408006",
|
||||
"MSRValue": "0x12",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "FRONTEND_RETIRED.LATENCY_GE_128",
|
||||
"EventName": "FRONTEND_RETIRED.L1I_MISS",
|
||||
"MSRIndex": "0x3F7",
|
||||
"TakenAlone": "1",
|
||||
"SampleAfterValue": "100007",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC6",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Retired Instructions who experienced decode stream buffer (DSB - the decoded instruction-cache) miss. Precise Event.",
|
||||
"PEBS": "1",
|
||||
"MSRValue": "0x11",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "FRONTEND_RETIRED.DSB_MISS",
|
||||
"MSRIndex": "0x3F7",
|
||||
"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
|
||||
"TakenAlone": "1",
|
||||
"SampleAfterValue": "100007",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC6",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall. Precise Event.",
|
||||
"PEBS": "1",
|
||||
"MSRValue": "0x300206",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_3",
|
||||
"MSRIndex": "0x3F7",
|
||||
"TakenAlone": "1",
|
||||
"SampleAfterValue": "100007",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC6",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall. Precise Event.",
|
||||
"PEBS": "1",
|
||||
"MSRValue": "0x100206",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1",
|
||||
"MSRIndex": "0x3F7",
|
||||
"PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.",
|
||||
"TakenAlone": "1",
|
||||
"SampleAfterValue": "100007",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC6",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall. Precise Event.",
|
||||
"PEBS": "1",
|
||||
"MSRValue": "0x420006",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "FRONTEND_RETIRED.LATENCY_GE_512",
|
||||
"MSRIndex": "0x3F7",
|
||||
"TakenAlone": "1",
|
||||
"SampleAfterValue": "100007",
|
||||
@ -442,11 +414,11 @@
|
||||
{
|
||||
"EventCode": "0xC6",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall. Precise Event.",
|
||||
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall. Precise Event.",
|
||||
"PEBS": "1",
|
||||
"MSRValue": "0x420006",
|
||||
"MSRValue": "0x408006",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "FRONTEND_RETIRED.LATENCY_GE_512",
|
||||
"EventName": "FRONTEND_RETIRED.LATENCY_GE_128",
|
||||
"MSRIndex": "0x3F7",
|
||||
"TakenAlone": "1",
|
||||
"SampleAfterValue": "100007",
|
||||
@ -455,13 +427,12 @@
|
||||
{
|
||||
"EventCode": "0xC6",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall. Precise Event.",
|
||||
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall. Precise Event.",
|
||||
"PEBS": "1",
|
||||
"MSRValue": "0x100206",
|
||||
"MSRValue": "0x404006",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1",
|
||||
"EventName": "FRONTEND_RETIRED.LATENCY_GE_64",
|
||||
"MSRIndex": "0x3F7",
|
||||
"PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.\r\n",
|
||||
"TakenAlone": "1",
|
||||
"SampleAfterValue": "100007",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
@ -469,12 +440,41 @@
|
||||
{
|
||||
"EventCode": "0xC6",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall. Precise Event.",
|
||||
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall. Precise Event.",
|
||||
"PEBS": "1",
|
||||
"MSRValue": "0x300206",
|
||||
"MSRValue": "0x402006",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_3",
|
||||
"EventName": "FRONTEND_RETIRED.LATENCY_GE_32",
|
||||
"MSRIndex": "0x3F7",
|
||||
"PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.",
|
||||
"TakenAlone": "1",
|
||||
"SampleAfterValue": "100007",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC6",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall. Precise Event.",
|
||||
"PEBS": "1",
|
||||
"MSRValue": "0x401006",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "FRONTEND_RETIRED.LATENCY_GE_16",
|
||||
"MSRIndex": "0x3F7",
|
||||
"PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.",
|
||||
"TakenAlone": "1",
|
||||
"SampleAfterValue": "100007",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC6",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.",
|
||||
"PEBS": "1",
|
||||
"MSRValue": "0x400806",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "FRONTEND_RETIRED.LATENCY_GE_8",
|
||||
"MSRIndex": "0x3F7",
|
||||
"PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops.",
|
||||
"TakenAlone": "1",
|
||||
"SampleAfterValue": "100007",
|
||||
"CounterHTOff": "0,1,2,3"
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,6 +1,5 @@
|
||||
[
|
||||
{
|
||||
"EventCode": "0x00",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Instructions retired from execution.",
|
||||
"Counter": "Fixed counter 0",
|
||||
@ -10,7 +9,6 @@
|
||||
"CounterHTOff": "Fixed counter 0"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x00",
|
||||
"UMask": "0x2",
|
||||
"BriefDescription": "Core cycles when the thread is not in halt state",
|
||||
"Counter": "Fixed counter 1",
|
||||
@ -20,7 +18,6 @@
|
||||
"CounterHTOff": "Fixed counter 1"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x00",
|
||||
"UMask": "0x2",
|
||||
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
|
||||
"Counter": "Fixed counter 1",
|
||||
@ -30,7 +27,6 @@
|
||||
"CounterHTOff": "Fixed counter 1"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x00",
|
||||
"UMask": "0x3",
|
||||
"BriefDescription": "Reference cycles when the core is not in halt state.",
|
||||
"Counter": "Fixed counter 2",
|
||||
@ -98,16 +94,6 @@
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x0E",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "UOPS_ISSUED.ANY",
|
||||
"PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"Invert": "1",
|
||||
"EventCode": "0x0E",
|
||||
@ -120,13 +106,23 @@
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x0E",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "UOPS_ISSUED.ANY",
|
||||
"PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x0E",
|
||||
"UMask": "0x2",
|
||||
"BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector registers.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH",
|
||||
"PublicDescription": "Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guide.",
|
||||
"PublicDescription": "Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to \u201cMixing Intel AVX and Intel SSE Code\u201d section of the Optimization Guide.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
@ -203,19 +199,19 @@
|
||||
{
|
||||
"EventCode": "0x3C",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Core crystal clock cycles when the thread is unhalted.",
|
||||
"BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is unhalted.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "CPU_CLK_UNHALTED.REF_XCLK",
|
||||
"EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
|
||||
"AnyThread": "1",
|
||||
"SampleAfterValue": "2503",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x3C",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is unhalted.",
|
||||
"BriefDescription": "Core crystal clock cycles when the thread is unhalted.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
|
||||
"AnyThread": "1",
|
||||
"EventName": "CPU_CLK_UNHALTED.REF_XCLK",
|
||||
"SampleAfterValue": "2503",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
@ -248,12 +244,12 @@
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x5E",
|
||||
"EventCode": "0x59",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
|
||||
"BriefDescription": "Cycles where the pipeline is stalled due to serializing operations.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "RS_EVENTS.EMPTY_CYCLES",
|
||||
"PublicDescription": "Counts cycles during which the reservation station (RS) is empty for the thread.; Note: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.",
|
||||
"EventName": "PARTIAL_RAT_STALLS.SCOREBOARD",
|
||||
"PublicDescription": "This event counts cycles during which the microcode scoreboard stalls happen.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
@ -270,6 +266,16 @@
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x5E",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "RS_EVENTS.EMPTY_CYCLES",
|
||||
"PublicDescription": "Counts cycles during which the reservation station (RS) is empty for the thread.; Note: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0x87",
|
||||
"UMask": "0x1",
|
||||
@ -361,12 +367,12 @@
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xA2",
|
||||
"EventCode": "0xa2",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Resource-related stall cycles",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "RESOURCE_STALLS.ANY",
|
||||
"PublicDescription": "Counts resource-related stall cycles. Reasons for stalls can be as follows:a. *any* u-arch structure got full (LB, SB, RS, ROB, BOB, LM, Physical Register Reclaim Table (PRRT), or Physical History Table (PHT) slots).b. *any* u-arch structure got empty (like INT/SIMD FreeLists).c. FPU control word (FPCW), MXCSR.and others. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.",
|
||||
"PublicDescription": "Counts resource-related stall cycles.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
@ -519,17 +525,6 @@
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xA8",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "LSD.CYCLES_ACTIVE",
|
||||
"CounterMask": "1",
|
||||
"PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xA8",
|
||||
"UMask": "0x1",
|
||||
@ -541,13 +536,58 @@
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xA8",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "LSD.CYCLES_ACTIVE",
|
||||
"CounterMask": "1",
|
||||
"PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB1",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
|
||||
"BriefDescription": "Cycles where at least 4 uops were executed per-thread",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "UOPS_EXECUTED.THREAD",
|
||||
"PublicDescription": "Number of uops to be executed per-thread each cycle.",
|
||||
"EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC",
|
||||
"CounterMask": "4",
|
||||
"PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB1",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Cycles where at least 3 uops were executed per-thread",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC",
|
||||
"CounterMask": "3",
|
||||
"PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB1",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Cycles where at least 2 uops were executed per-thread",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC",
|
||||
"CounterMask": "2",
|
||||
"PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB1",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Cycles where at least 1 uop was executed per-thread",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC",
|
||||
"CounterMask": "1",
|
||||
"PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
@ -566,44 +606,10 @@
|
||||
{
|
||||
"EventCode": "0xB1",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Cycles where at least 1 uop was executed per-thread",
|
||||
"BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC",
|
||||
"CounterMask": "1",
|
||||
"PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB1",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Cycles where at least 2 uops were executed per-thread",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC",
|
||||
"CounterMask": "2",
|
||||
"PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB1",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Cycles where at least 3 uops were executed per-thread",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC",
|
||||
"CounterMask": "3",
|
||||
"PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xB1",
|
||||
"UMask": "0x1",
|
||||
"BriefDescription": "Cycles where at least 4 uops were executed per-thread",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC",
|
||||
"CounterMask": "4",
|
||||
"PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
|
||||
"EventName": "UOPS_EXECUTED.THREAD",
|
||||
"PublicDescription": "Number of uops to be executed per-thread each cycle.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
@ -618,11 +624,12 @@
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"Invert": "1",
|
||||
"EventCode": "0xB1",
|
||||
"UMask": "0x2",
|
||||
"BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
|
||||
"BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
|
||||
"EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
|
||||
"CounterMask": "1",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
@ -630,10 +637,10 @@
|
||||
{
|
||||
"EventCode": "0xB1",
|
||||
"UMask": "0x2",
|
||||
"BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
|
||||
"BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
|
||||
"CounterMask": "2",
|
||||
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
|
||||
"CounterMask": "4",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
@ -650,20 +657,19 @@
|
||||
{
|
||||
"EventCode": "0xB1",
|
||||
"UMask": "0x2",
|
||||
"BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
|
||||
"BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
|
||||
"CounterMask": "4",
|
||||
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
|
||||
"CounterMask": "2",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"Invert": "1",
|
||||
"EventCode": "0xB1",
|
||||
"UMask": "0x2",
|
||||
"BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
|
||||
"BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
|
||||
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
|
||||
"CounterMask": "1",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
@ -724,28 +730,6 @@
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC2",
|
||||
"UMask": "0x2",
|
||||
"BriefDescription": "Retirement slots used.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "UOPS_RETIRED.RETIRE_SLOTS",
|
||||
"PublicDescription": "Counts the retirement slots used.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"Invert": "1",
|
||||
"EventCode": "0xC2",
|
||||
"UMask": "0x2",
|
||||
"BriefDescription": "Cycles without actually retired uops.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "UOPS_RETIRED.STALL_CYCLES",
|
||||
"CounterMask": "1",
|
||||
"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts cycles without actually retired uops.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"Invert": "1",
|
||||
"EventCode": "0xC2",
|
||||
@ -758,6 +742,28 @@
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"Invert": "1",
|
||||
"EventCode": "0xC2",
|
||||
"UMask": "0x2",
|
||||
"BriefDescription": "Cycles without actually retired uops.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "UOPS_RETIRED.STALL_CYCLES",
|
||||
"CounterMask": "1",
|
||||
"PublicDescription": "This event counts cycles without actually retired uops.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xC2",
|
||||
"UMask": "0x2",
|
||||
"BriefDescription": "Retirement slots used.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "UOPS_RETIRED.RETIRE_SLOTS",
|
||||
"PublicDescription": "Counts the retirement slots used.",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EdgeDetect": "1",
|
||||
"EventCode": "0xC3",
|
||||
@ -766,6 +772,7 @@
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "MACHINE_CLEARS.COUNT",
|
||||
"CounterMask": "1",
|
||||
"PublicDescription": "Number of machine clears (nukes) of any type.",
|
||||
"SampleAfterValue": "100003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
@ -841,11 +848,12 @@
|
||||
{
|
||||
"EventCode": "0xC4",
|
||||
"UMask": "0x10",
|
||||
"BriefDescription": "Not taken branch instructions retired.",
|
||||
"BriefDescription": "Counts all not taken macro branch instructions retired.",
|
||||
"PEBS": "1",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "BR_INST_RETIRED.NOT_TAKEN",
|
||||
"Errata": "SKL091",
|
||||
"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts not taken branch instructions retired.",
|
||||
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts not taken branch instructions retired.",
|
||||
"SampleAfterValue": "400009",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
@ -937,6 +945,15 @@
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xCC",
|
||||
"UMask": "0x40",
|
||||
"BriefDescription": "Number of retired PAUSE instructions (that do not end up with a VMExit to the VMM; TSX aborted Instructions may be counted). This event is not supported on first SKL and KBL products.",
|
||||
"Counter": "0,1,2,3",
|
||||
"EventName": "ROB_MISC_EVENTS.PAUSE_INST",
|
||||
"SampleAfterValue": "2000003",
|
||||
"CounterHTOff": "0,1,2,3,4,5,6,7"
|
||||
},
|
||||
{
|
||||
"EventCode": "0xE6",
|
||||
"UMask": "0x1",
|
||||
|
||||
Loading…
Reference in New Issue
Block a user