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drm/i915/crt: Flush register prior to waiting for vblank.

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If we don't flush the write then we can not be sure that the border
colour will have taken effect by the time we try to read it back.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Chris Wilson 2010-08-09 14:50:53 +01:00
parent 82d7c9e7da
commit 19c55da116
1 changed files with 1 additions and 0 deletions
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drivers/gpu/drm/i915/intel_crt.c
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@ -327,6 +327,7 @@ intel_crt_load_detect(struct drm_crtc *crtc, struct intel_encoder *intel_encoder
if (IS_I9XX(dev)) {
uint32_t pipeconf = I915_READ(pipeconf_reg);
I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
POSTING_READ(pipeconf_reg);
/* Wait for next Vblank to substitue
* border color for Color info */
intel_wait_for_vblank(dev, pipe);