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x86/speculation: Prepare entry code for Spectre v1 swapgs mitigations
Spectre v1 isn't only about array bounds checks. It can affect any conditional checks. The kernel entry code interrupt, exception, and NMI handlers all have conditional swapgs checks. Those may be problematic in the context of Spectre v1, as kernel code can speculatively run with a user GS. For example: if (coming from user space) swapgs mov %gs:<percpu_offset>, %reg mov (%reg), %reg1 When coming from user space, the CPU can speculatively skip the swapgs, and then do a speculative percpu load using the user GS value. So the user can speculatively force a read of any kernel value. If a gadget exists which uses the percpu value as an address in another load/store, then the contents of the kernel value may become visible via an L1 side channel attack. A similar attack exists when coming from kernel space. The CPU can speculatively do the swapgs, causing the user GS to get used for the rest of the speculative window. The mitigation is similar to a traditional Spectre v1 mitigation, except: a) index masking isn't possible; because the index (percpu offset) isn't user-controlled; and b) an lfence is needed in both the "from user" swapgs path and the "from kernel" non-swapgs path (because of the two attacks described above). The user entry swapgs paths already have SWITCH_TO_KERNEL_CR3, which has a CR3 write when PTI is enabled. Since CR3 writes are serializing, the lfences can be skipped in those cases. On the other hand, the kernel entry swapgs paths don't depend on PTI. To avoid unnecessary lfences for the user entry case, create two separate features for alternative patching: X86_FEATURE_FENCE_SWAPGS_USER X86_FEATURE_FENCE_SWAPGS_KERNEL Use these features in entry code to patch in lfences where needed. The features aren't enabled yet, so there's no functional change. Signed-off-by: Josh Poimboeuf <jpoimboe@redhat.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Dave Hansen <dave.hansen@intel.com>
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@ -314,6 +314,23 @@ For 32-bit we have the following conventions - kernel is built with
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#endif
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/*
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* Mitigate Spectre v1 for conditional swapgs code paths.
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*
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* FENCE_SWAPGS_USER_ENTRY is used in the user entry swapgs code path, to
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* prevent a speculative swapgs when coming from kernel space.
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*
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* FENCE_SWAPGS_KERNEL_ENTRY is used in the kernel entry non-swapgs code path,
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* to prevent the swapgs from getting speculatively skipped when coming from
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* user space.
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*/
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.macro FENCE_SWAPGS_USER_ENTRY
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ALTERNATIVE "", "lfence", X86_FEATURE_FENCE_SWAPGS_USER
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.endm
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.macro FENCE_SWAPGS_KERNEL_ENTRY
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ALTERNATIVE "", "lfence", X86_FEATURE_FENCE_SWAPGS_KERNEL
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.endm
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.macro STACKLEAK_ERASE_NOCLOBBER
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#ifdef CONFIG_GCC_PLUGIN_STACKLEAK
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PUSH_AND_CLEAR_REGS
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@ -519,7 +519,7 @@ ENTRY(interrupt_entry)
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testb $3, CS-ORIG_RAX+8(%rsp)
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jz 1f
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SWAPGS
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FENCE_SWAPGS_USER_ENTRY
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/*
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* Switch to the thread stack. The IRET frame and orig_ax are
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* on the stack, as well as the return address. RDI..R12 are
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@ -549,8 +549,10 @@ ENTRY(interrupt_entry)
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UNWIND_HINT_FUNC
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movq (%rdi), %rdi
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jmpq 2f
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1:
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FENCE_SWAPGS_KERNEL_ENTRY
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2:
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PUSH_AND_CLEAR_REGS save_ret=1
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ENCODE_FRAME_POINTER 8
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@ -1221,6 +1223,13 @@ ENTRY(paranoid_entry)
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*/
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SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg=%rax save_reg=%r14
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/*
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* The above SAVE_AND_SWITCH_TO_KERNEL_CR3 macro doesn't do an
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* unconditional CR3 write, even in the PTI case. So do an lfence
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* to prevent GS speculation, regardless of whether PTI is enabled.
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*/
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FENCE_SWAPGS_KERNEL_ENTRY
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ret
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END(paranoid_entry)
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@ -1271,6 +1280,7 @@ ENTRY(error_entry)
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* from user mode due to an IRET fault.
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*/
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SWAPGS
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FENCE_SWAPGS_USER_ENTRY
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/* We have user CR3. Change to kernel CR3. */
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SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
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@ -1292,6 +1302,8 @@ ENTRY(error_entry)
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CALL_enter_from_user_mode
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ret
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.Lerror_entry_done_lfence:
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FENCE_SWAPGS_KERNEL_ENTRY
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.Lerror_entry_done:
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TRACE_IRQS_OFF
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ret
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@ -1310,7 +1322,7 @@ ENTRY(error_entry)
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cmpq %rax, RIP+8(%rsp)
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je .Lbstep_iret
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cmpq $.Lgs_change, RIP+8(%rsp)
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jne .Lerror_entry_done
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jne .Lerror_entry_done_lfence
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/*
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* hack: .Lgs_change can fail with user gsbase. If this happens, fix up
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@ -1318,6 +1330,7 @@ ENTRY(error_entry)
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* .Lgs_change's error handler with kernel gsbase.
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*/
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SWAPGS
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FENCE_SWAPGS_USER_ENTRY
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SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
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jmp .Lerror_entry_done
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@ -1332,6 +1345,7 @@ ENTRY(error_entry)
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* gsbase and CR3. Switch to kernel gsbase and CR3:
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*/
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SWAPGS
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FENCE_SWAPGS_USER_ENTRY
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SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
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/*
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@ -1423,6 +1437,7 @@ ENTRY(nmi)
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swapgs
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cld
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FENCE_SWAPGS_USER_ENTRY
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SWITCH_TO_KERNEL_CR3 scratch_reg=%rdx
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movq %rsp, %rdx
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movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp
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@ -281,6 +281,8 @@
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#define X86_FEATURE_CQM_OCCUP_LLC (11*32+ 1) /* LLC occupancy monitoring */
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#define X86_FEATURE_CQM_MBM_TOTAL (11*32+ 2) /* LLC Total MBM monitoring */
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#define X86_FEATURE_CQM_MBM_LOCAL (11*32+ 3) /* LLC Local MBM monitoring */
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#define X86_FEATURE_FENCE_SWAPGS_USER (11*32+ 4) /* "" LFENCE in user entry SWAPGS path */
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#define X86_FEATURE_FENCE_SWAPGS_KERNEL (11*32+ 5) /* "" LFENCE in kernel entry SWAPGS path */
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/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
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#define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */
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