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ALSA: hda: cleanup definitions for multi-link registers
For some reason two masks are used without the AZX prefix, and the pattern MLCLT should be ML_LCTL for consistency. Pure rename, no functionality change. Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Reviewed-by: Rander Wang <rander.wang@intel.com> Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com> Link: https://lore.kernel.org/r/20220822190044.170495-1-pierre-louis.bossart@linux.intel.com Signed-off-by: Takashi Iwai <tiwai@suse.de>
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@ -260,7 +260,18 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
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#define AZX_REG_ML_LCAP 0x00
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#define AZX_REG_ML_LCTL 0x04
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#define AZX_ML_LCTL_CPA BIT(23)
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#define AZX_ML_LCTL_CPA_SHIFT 23
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#define AZX_ML_LCTL_SPA BIT(16)
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#define AZX_ML_LCTL_SPA_SHIFT 16
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#define AZX_ML_LCTL_SCF GENMASK(3, 0)
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#define AZX_REG_ML_LOSIDV 0x08
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/* bit0 is reserved, with BIT(1) mapping to stream1 */
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#define AZX_ML_LOSIDV_STREAM_MASK 0xFFFE
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#define AZX_REG_ML_LSDIID 0x0C
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#define AZX_REG_ML_LPSOO 0x10
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#define AZX_REG_ML_LPSIO 0x12
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@ -268,15 +279,6 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
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#define AZX_REG_ML_LOUTPAY 0x20
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#define AZX_REG_ML_LINPAY 0x30
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/* bit0 is reserved, with BIT(1) mapping to stream1 */
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#define ML_LOSIDV_STREAM_MASK 0xFFFE
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#define ML_LCTL_SCF_MASK 0xF
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#define AZX_MLCTL_SPA (0x1 << 16)
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#define AZX_MLCTL_CPA (0x1 << 23)
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#define AZX_MLCTL_SPA_SHIFT 16
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#define AZX_MLCTL_CPA_SHIFT 23
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/* registers for DMA Resume Capability Structure */
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#define AZX_DRSM_CAP_ID 0x5
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#define AZX_REG_DRSM_CTL 0x4
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@ -170,7 +170,7 @@ static int check_hdac_link_power_active(struct hdac_ext_link *link, bool enable)
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{
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int timeout;
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u32 val;
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int mask = (1 << AZX_MLCTL_CPA_SHIFT);
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int mask = (1 << AZX_ML_LCTL_CPA_SHIFT);
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udelay(3);
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timeout = 150;
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@ -178,10 +178,10 @@ static int check_hdac_link_power_active(struct hdac_ext_link *link, bool enable)
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do {
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val = readl(link->ml_addr + AZX_REG_ML_LCTL);
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if (enable) {
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if (((val & mask) >> AZX_MLCTL_CPA_SHIFT))
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if (((val & mask) >> AZX_ML_LCTL_CPA_SHIFT))
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return 0;
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} else {
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if (!((val & mask) >> AZX_MLCTL_CPA_SHIFT))
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if (!((val & mask) >> AZX_ML_LCTL_CPA_SHIFT))
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return 0;
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}
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udelay(3);
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@ -197,7 +197,7 @@ static int check_hdac_link_power_active(struct hdac_ext_link *link, bool enable)
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int snd_hdac_ext_bus_link_power_up(struct hdac_ext_link *link)
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{
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snd_hdac_updatel(link->ml_addr, AZX_REG_ML_LCTL,
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AZX_MLCTL_SPA, AZX_MLCTL_SPA);
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AZX_ML_LCTL_SPA, AZX_ML_LCTL_SPA);
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return check_hdac_link_power_active(link, true);
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}
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@ -209,7 +209,7 @@ EXPORT_SYMBOL_GPL(snd_hdac_ext_bus_link_power_up);
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*/
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int snd_hdac_ext_bus_link_power_down(struct hdac_ext_link *link)
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{
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snd_hdac_updatel(link->ml_addr, AZX_REG_ML_LCTL, AZX_MLCTL_SPA, 0);
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snd_hdac_updatel(link->ml_addr, AZX_REG_ML_LCTL, AZX_ML_LCTL_SPA, 0);
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return check_hdac_link_power_active(link, false);
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}
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@ -226,7 +226,7 @@ int snd_hdac_ext_bus_link_power_up_all(struct hdac_bus *bus)
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list_for_each_entry(hlink, &bus->hlink_list, list) {
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snd_hdac_updatel(hlink->ml_addr, AZX_REG_ML_LCTL,
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AZX_MLCTL_SPA, AZX_MLCTL_SPA);
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AZX_ML_LCTL_SPA, AZX_ML_LCTL_SPA);
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ret = check_hdac_link_power_active(hlink, true);
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if (ret < 0)
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return ret;
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@ -247,7 +247,7 @@ int snd_hdac_ext_bus_link_power_down_all(struct hdac_bus *bus)
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list_for_each_entry(hlink, &bus->hlink_list, list) {
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snd_hdac_updatel(hlink->ml_addr, AZX_REG_ML_LCTL,
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AZX_MLCTL_SPA, 0);
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AZX_ML_LCTL_SPA, 0);
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ret = check_hdac_link_power_active(hlink, false);
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if (ret < 0)
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return ret;
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@ -281,7 +281,7 @@ int snd_hdac_ext_bus_link_get(struct hdac_bus *bus,
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* clear the register to invalidate all the output streams
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*/
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snd_hdac_updatew(link->ml_addr, AZX_REG_ML_LOSIDV,
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ML_LOSIDV_STREAM_MASK, 0);
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AZX_ML_LOSIDV_STREAM_MASK, 0);
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/*
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* wait for 521usec for codec to report status
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* HDA spec section 4.3 - Codec Discovery
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@ -489,14 +489,14 @@ static int intel_ml_lctl_set_power(struct azx *chip, int state)
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* If other links are enabled for stream, they need similar fix
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*/
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val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
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val &= ~AZX_MLCTL_SPA;
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val |= state << AZX_MLCTL_SPA_SHIFT;
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val &= ~AZX_ML_LCTL_SPA;
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val |= state << AZX_ML_LCTL_SPA_SHIFT;
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writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
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/* wait for CPA */
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timeout = 50;
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while (timeout) {
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if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
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AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
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AZX_ML_LCTL_CPA) == (state << AZX_ML_LCTL_CPA_SHIFT))
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return 0;
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timeout--;
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udelay(10);
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@ -514,15 +514,15 @@ static void intel_init_lctl(struct azx *chip)
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/* 0. check lctl register value is correct or not */
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val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
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/* if SCF is already set, let's use it */
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if ((val & ML_LCTL_SCF_MASK) != 0)
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if ((val & AZX_ML_LCTL_SCF) != 0)
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return;
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/*
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* Before operating on SPA, CPA must match SPA.
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* Any deviation may result in undefined behavior.
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*/
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if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
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((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
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if (((val & AZX_ML_LCTL_SPA) >> AZX_ML_LCTL_SPA_SHIFT) !=
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((val & AZX_ML_LCTL_CPA) >> AZX_ML_LCTL_CPA_SHIFT))
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return;
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/* 1. turn link down: set SPA to 0 and wait CPA to 0 */
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@ -532,7 +532,7 @@ static void intel_init_lctl(struct azx *chip)
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goto set_spa;
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/* 2. update SCF to select a properly audio clock*/
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val &= ~ML_LCTL_SCF_MASK;
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val &= ~AZX_ML_LCTL_SCF;
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val |= intel_get_lctl_scf(chip);
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writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
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