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[media] ds3000: clean up in tune procedure
Variable 'retune' does not make sense. Loop is not needed for only one try. Remove unnecessary dprintk's. Remove a lot of debug messages and delays. Signed-off-by: Igor M. Liplianin <liplianin@me.by> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Igor M. Liplianin
Mauro Carvalho Chehab
parent
2f30fb49c3
commit
18a73f36a2
@ -536,25 +536,6 @@ static int ds3000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
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return 0;
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}
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static void ds3000_dump_registers(struct dvb_frontend *fe)
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{
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struct ds3000_state *state = fe->demodulator_priv;
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int x, y, reg = 0, val;
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for (y = 0; y < 16; y++) {
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dprintk("%s: %02x: ", __func__, y);
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for (x = 0; x < 16; x++) {
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reg = (y << 4) + x;
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val = ds3000_readreg(state, reg);
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if (x != 15)
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dprintk("%02x ", val);
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else
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dprintk("%02x\n", val);
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}
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}
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dprintk("%s: -- DS3000 DUMP DONE --\n", __func__);
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}
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static int ds3000_read_status(struct dvb_frontend *fe, fe_status_t* status)
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{
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struct ds3000_state *state = fe->demodulator_priv;
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@ -589,16 +570,6 @@ static int ds3000_read_status(struct dvb_frontend *fe, fe_status_t* status)
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return 0;
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}
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#define FE_IS_TUNED (FE_HAS_SIGNAL + FE_HAS_LOCK)
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static int ds3000_is_tuned(struct dvb_frontend *fe)
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{
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fe_status_t tunerstat;
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ds3000_read_status(fe, &tunerstat);
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return ((tunerstat & FE_IS_TUNED) == FE_IS_TUNED);
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}
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/* read DS3000 BER value */
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static int ds3000_read_ber(struct dvb_frontend *fe, u32* ber)
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{
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@ -1049,7 +1020,7 @@ static int ds3000_tune(struct dvb_frontend *fe,
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struct ds3000_state *state = fe->demodulator_priv;
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struct dtv_frontend_properties *c = &fe->dtv_property_cache;
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int ret = 0, retune, i;
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int i;
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u8 status, mlpf, mlpf_new, mlpf_max, mlpf_min, nlpf;
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u16 value, ndiv;
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u32 f3db;
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@ -1072,252 +1043,235 @@ static int ds3000_tune(struct dvb_frontend *fe,
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/* discard the 'current' tuning parameters and prepare to tune */
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ds3000_clone_params(fe);
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retune = 1; /* try 1 times */
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dprintk("%s: retune = %d\n", __func__, retune);
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dprintk("%s: frequency = %d\n", __func__, state->dcur.frequency);
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dprintk("%s: symbol_rate = %d\n", __func__, state->dcur.symbol_rate);
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dprintk("%s: FEC = %d \n", __func__,
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state->dcur.fec);
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dprintk("%s: Inversion = %d\n", __func__, state->dcur.inversion);
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/* Reset status register */
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status = 0;
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/* Tune */
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/* unknown */
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ds3000_tuner_writereg(state, 0x07, 0x02);
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ds3000_tuner_writereg(state, 0x10, 0x00);
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ds3000_tuner_writereg(state, 0x60, 0x79);
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ds3000_tuner_writereg(state, 0x08, 0x01);
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ds3000_tuner_writereg(state, 0x00, 0x01);
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/* calculate and set freq divider */
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if (state->dcur.frequency < 1146000) {
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ds3000_tuner_writereg(state, 0x10, 0x11);
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ndiv = ((state->dcur.frequency * (6 + 8) * 4) +
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(DS3000_XTAL_FREQ / 2)) /
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DS3000_XTAL_FREQ - 1024;
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} else {
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ds3000_tuner_writereg(state, 0x10, 0x01);
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ndiv = ((state->dcur.frequency * (6 + 8) * 2) +
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(DS3000_XTAL_FREQ / 2)) /
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DS3000_XTAL_FREQ - 1024;
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}
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do {
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/* Reset status register */
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status = 0;
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/* Tune */
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/* unknown */
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ds3000_tuner_writereg(state, 0x07, 0x02);
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ds3000_tuner_writereg(state, 0x10, 0x00);
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ds3000_tuner_writereg(state, 0x60, 0x79);
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ds3000_tuner_writereg(state, 0x08, 0x01);
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ds3000_tuner_writereg(state, 0x00, 0x01);
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/* calculate and set freq divider */
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if (state->dcur.frequency < 1146000) {
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ds3000_tuner_writereg(state, 0x10, 0x11);
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ndiv = ((state->dcur.frequency * (6 + 8) * 4) +
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(DS3000_XTAL_FREQ / 2)) /
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DS3000_XTAL_FREQ - 1024;
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} else {
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ds3000_tuner_writereg(state, 0x10, 0x01);
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ndiv = ((state->dcur.frequency * (6 + 8) * 2) +
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(DS3000_XTAL_FREQ / 2)) /
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DS3000_XTAL_FREQ - 1024;
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}
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ds3000_tuner_writereg(state, 0x01, (ndiv & 0x0f00) >> 8);
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ds3000_tuner_writereg(state, 0x02, ndiv & 0x00ff);
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ds3000_tuner_writereg(state, 0x01, (ndiv & 0x0f00) >> 8);
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ds3000_tuner_writereg(state, 0x02, ndiv & 0x00ff);
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/* set pll */
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ds3000_tuner_writereg(state, 0x03, 0x06);
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ds3000_tuner_writereg(state, 0x51, 0x0f);
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ds3000_tuner_writereg(state, 0x51, 0x1f);
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ds3000_tuner_writereg(state, 0x50, 0x10);
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ds3000_tuner_writereg(state, 0x50, 0x00);
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msleep(5);
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/* set pll */
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ds3000_tuner_writereg(state, 0x03, 0x06);
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ds3000_tuner_writereg(state, 0x51, 0x0f);
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ds3000_tuner_writereg(state, 0x51, 0x1f);
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ds3000_tuner_writereg(state, 0x50, 0x10);
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ds3000_tuner_writereg(state, 0x50, 0x00);
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msleep(5);
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/* unknown */
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ds3000_tuner_writereg(state, 0x51, 0x17);
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ds3000_tuner_writereg(state, 0x51, 0x1f);
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ds3000_tuner_writereg(state, 0x50, 0x08);
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ds3000_tuner_writereg(state, 0x50, 0x00);
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msleep(5);
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/* unknown */
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ds3000_tuner_writereg(state, 0x51, 0x17);
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ds3000_tuner_writereg(state, 0x51, 0x1f);
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ds3000_tuner_writereg(state, 0x50, 0x08);
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ds3000_tuner_writereg(state, 0x50, 0x00);
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msleep(5);
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value = ds3000_tuner_readreg(state, 0x3d);
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value &= 0x0f;
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if ((value > 4) && (value < 15)) {
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value -= 3;
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if (value < 4)
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value = 4;
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value = ((value << 3) | 0x01) & 0x79;
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}
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value = ds3000_tuner_readreg(state, 0x3d);
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value &= 0x0f;
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if ((value > 4) && (value < 15)) {
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value -= 3;
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if (value < 4)
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value = 4;
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value = ((value << 3) | 0x01) & 0x79;
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}
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ds3000_tuner_writereg(state, 0x60, value);
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ds3000_tuner_writereg(state, 0x51, 0x17);
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ds3000_tuner_writereg(state, 0x51, 0x1f);
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ds3000_tuner_writereg(state, 0x50, 0x08);
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ds3000_tuner_writereg(state, 0x50, 0x00);
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ds3000_tuner_writereg(state, 0x60, value);
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ds3000_tuner_writereg(state, 0x51, 0x17);
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ds3000_tuner_writereg(state, 0x51, 0x1f);
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ds3000_tuner_writereg(state, 0x50, 0x08);
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ds3000_tuner_writereg(state, 0x50, 0x00);
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/* set low-pass filter period */
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ds3000_tuner_writereg(state, 0x04, 0x2e);
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ds3000_tuner_writereg(state, 0x51, 0x1b);
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ds3000_tuner_writereg(state, 0x51, 0x1f);
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ds3000_tuner_writereg(state, 0x50, 0x04);
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ds3000_tuner_writereg(state, 0x50, 0x00);
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msleep(5);
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/* set low-pass filter period */
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ds3000_tuner_writereg(state, 0x04, 0x2e);
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ds3000_tuner_writereg(state, 0x51, 0x1b);
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ds3000_tuner_writereg(state, 0x51, 0x1f);
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ds3000_tuner_writereg(state, 0x50, 0x04);
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ds3000_tuner_writereg(state, 0x50, 0x00);
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msleep(5);
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f3db = ((state->dcur.symbol_rate / 1000) << 2) / 5 + 2000;
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if ((state->dcur.symbol_rate / 1000) < 5000)
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f3db += 3000;
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if (f3db < 7000)
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f3db = 7000;
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if (f3db > 40000)
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f3db = 40000;
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f3db = ((state->dcur.symbol_rate / 1000) << 2) / 5 + 2000;
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if ((state->dcur.symbol_rate / 1000) < 5000)
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f3db += 3000;
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if (f3db < 7000)
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f3db = 7000;
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if (f3db > 40000)
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f3db = 40000;
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/* set low-pass filter baseband */
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value = ds3000_tuner_readreg(state, 0x26);
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mlpf = 0x2e * 207 / ((value << 1) + 151);
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mlpf_max = mlpf * 135 / 100;
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mlpf_min = mlpf * 78 / 100;
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if (mlpf_max > 63)
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mlpf_max = 63;
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/* set low-pass filter baseband */
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value = ds3000_tuner_readreg(state, 0x26);
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mlpf = 0x2e * 207 / ((value << 1) + 151);
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mlpf_max = mlpf * 135 / 100;
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mlpf_min = mlpf * 78 / 100;
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if (mlpf_max > 63)
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mlpf_max = 63;
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/* rounded to the closest integer */
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nlpf = ((mlpf * f3db * 1000) + (2766 * DS3000_XTAL_FREQ / 2))
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/ (2766 * DS3000_XTAL_FREQ);
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if (nlpf > 23)
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nlpf = 23;
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if (nlpf < 1)
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nlpf = 1;
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/* rounded to the closest integer */
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nlpf = ((mlpf * f3db * 1000) + (2766 * DS3000_XTAL_FREQ / 2))
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/ (2766 * DS3000_XTAL_FREQ);
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if (nlpf > 23)
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nlpf = 23;
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if (nlpf < 1)
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nlpf = 1;
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/* rounded to the closest integer */
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mlpf_new = ((DS3000_XTAL_FREQ * nlpf * 2766) +
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(1000 * f3db / 2)) / (1000 * f3db);
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/* rounded to the closest integer */
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if (mlpf_new < mlpf_min) {
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nlpf++;
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mlpf_new = ((DS3000_XTAL_FREQ * nlpf * 2766) +
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(1000 * f3db / 2)) / (1000 * f3db);
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}
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if (mlpf_new < mlpf_min) {
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nlpf++;
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mlpf_new = ((DS3000_XTAL_FREQ * nlpf * 2766) +
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(1000 * f3db / 2)) / (1000 * f3db);
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}
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if (mlpf_new > mlpf_max)
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mlpf_new = mlpf_max;
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if (mlpf_new > mlpf_max)
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mlpf_new = mlpf_max;
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ds3000_tuner_writereg(state, 0x04, mlpf_new);
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ds3000_tuner_writereg(state, 0x06, nlpf);
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ds3000_tuner_writereg(state, 0x51, 0x1b);
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ds3000_tuner_writereg(state, 0x51, 0x1f);
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ds3000_tuner_writereg(state, 0x50, 0x04);
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ds3000_tuner_writereg(state, 0x50, 0x00);
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msleep(5);
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ds3000_tuner_writereg(state, 0x04, mlpf_new);
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ds3000_tuner_writereg(state, 0x06, nlpf);
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ds3000_tuner_writereg(state, 0x51, 0x1b);
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ds3000_tuner_writereg(state, 0x51, 0x1f);
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ds3000_tuner_writereg(state, 0x50, 0x04);
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ds3000_tuner_writereg(state, 0x50, 0x00);
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msleep(5);
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/* unknown */
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ds3000_tuner_writereg(state, 0x51, 0x1e);
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ds3000_tuner_writereg(state, 0x51, 0x1f);
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ds3000_tuner_writereg(state, 0x50, 0x01);
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ds3000_tuner_writereg(state, 0x50, 0x00);
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msleep(60);
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/* unknown */
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ds3000_tuner_writereg(state, 0x51, 0x1e);
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ds3000_tuner_writereg(state, 0x51, 0x1f);
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ds3000_tuner_writereg(state, 0x50, 0x01);
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ds3000_tuner_writereg(state, 0x50, 0x00);
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msleep(60);
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/* ds3000 global reset */
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ds3000_writereg(state, 0x07, 0x80);
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ds3000_writereg(state, 0x07, 0x00);
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/* ds3000 build-in uC reset */
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ds3000_writereg(state, 0xb2, 0x01);
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/* ds3000 software reset */
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ds3000_writereg(state, 0x00, 0x01);
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/* ds3000 global reset */
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ds3000_writereg(state, 0x07, 0x80);
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ds3000_writereg(state, 0x07, 0x00);
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/* ds3000 build-in uC reset */
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ds3000_writereg(state, 0xb2, 0x01);
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/* ds3000 software reset */
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ds3000_writereg(state, 0x00, 0x01);
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switch (c->delivery_system) {
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case SYS_DVBS:
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/* initialise the demod in DVB-S mode */
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for (i = 0; i < sizeof(ds3000_dvbs_init_tab); i += 2)
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ds3000_writereg(state,
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ds3000_dvbs_init_tab[i],
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ds3000_dvbs_init_tab[i + 1]);
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value = ds3000_readreg(state, 0xfe);
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value &= 0xc0;
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value |= 0x1b;
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ds3000_writereg(state, 0xfe, value);
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break;
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case SYS_DVBS2:
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/* initialise the demod in DVB-S2 mode */
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for (i = 0; i < sizeof(ds3000_dvbs2_init_tab); i += 2)
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ds3000_writereg(state,
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ds3000_dvbs2_init_tab[i],
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ds3000_dvbs2_init_tab[i + 1]);
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ds3000_writereg(state, 0xfe, 0x98);
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break;
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default:
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return 1;
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}
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/* enable 27MHz clock output */
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ds3000_writereg(state, 0x29, 0x80);
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/* enable ac coupling */
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ds3000_writereg(state, 0x25, 0x8a);
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/* enhance symbol rate performance */
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if ((state->dcur.symbol_rate / 1000) <= 5000) {
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value = 29777 / (state->dcur.symbol_rate / 1000) + 1;
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if (value % 2 != 0)
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value++;
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ds3000_writereg(state, 0xc3, 0x0d);
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ds3000_writereg(state, 0xc8, value);
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ds3000_writereg(state, 0xc4, 0x10);
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ds3000_writereg(state, 0xc7, 0x0e);
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} else if ((state->dcur.symbol_rate / 1000) <= 10000) {
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value = 92166 / (state->dcur.symbol_rate / 1000) + 1;
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if (value % 2 != 0)
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value++;
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ds3000_writereg(state, 0xc3, 0x07);
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ds3000_writereg(state, 0xc8, value);
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ds3000_writereg(state, 0xc4, 0x09);
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ds3000_writereg(state, 0xc7, 0x12);
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} else if ((state->dcur.symbol_rate / 1000) <= 20000) {
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value = 64516 / (state->dcur.symbol_rate / 1000) + 1;
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ds3000_writereg(state, 0xc3, value);
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ds3000_writereg(state, 0xc8, 0x0e);
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ds3000_writereg(state, 0xc4, 0x07);
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ds3000_writereg(state, 0xc7, 0x18);
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} else {
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value = 129032 / (state->dcur.symbol_rate / 1000) + 1;
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ds3000_writereg(state, 0xc3, value);
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ds3000_writereg(state, 0xc8, 0x0a);
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ds3000_writereg(state, 0xc4, 0x05);
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ds3000_writereg(state, 0xc7, 0x24);
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}
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/* normalized symbol rate rounded to the closest integer */
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value = (((state->dcur.symbol_rate / 1000) << 16) +
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(DS3000_SAMPLE_RATE / 2)) / DS3000_SAMPLE_RATE;
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ds3000_writereg(state, 0x61, value & 0x00ff);
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ds3000_writereg(state, 0x62, (value & 0xff00) >> 8);
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/* co-channel interference cancellation disabled */
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ds3000_writereg(state, 0x56, 0x00);
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/* equalizer disabled */
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ds3000_writereg(state, 0x76, 0x00);
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/*ds3000_writereg(state, 0x08, 0x03);
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ds3000_writereg(state, 0xfd, 0x22);
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ds3000_writereg(state, 0x08, 0x07);
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ds3000_writereg(state, 0xfd, 0x42);
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ds3000_writereg(state, 0x08, 0x07);*/
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if (state->config->ci_mode) {
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switch (c->delivery_system) {
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case SYS_DVBS:
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/* initialise the demod in DVB-S mode */
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for (i = 0; i < sizeof(ds3000_dvbs_init_tab); i += 2)
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ds3000_writereg(state,
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ds3000_dvbs_init_tab[i],
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ds3000_dvbs_init_tab[i + 1]);
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value = ds3000_readreg(state, 0xfe);
|
||||
value &= 0xc0;
|
||||
value |= 0x1b;
|
||||
ds3000_writereg(state, 0xfe, value);
|
||||
break;
|
||||
case SYS_DVBS2:
|
||||
/* initialise the demod in DVB-S2 mode */
|
||||
for (i = 0; i < sizeof(ds3000_dvbs2_init_tab); i += 2)
|
||||
ds3000_writereg(state,
|
||||
ds3000_dvbs2_init_tab[i],
|
||||
ds3000_dvbs2_init_tab[i + 1]);
|
||||
ds3000_writereg(state, 0xfe, 0x98);
|
||||
break;
|
||||
default:
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* enable 27MHz clock output */
|
||||
ds3000_writereg(state, 0x29, 0x80);
|
||||
/* enable ac coupling */
|
||||
ds3000_writereg(state, 0x25, 0x8a);
|
||||
|
||||
/* enhance symbol rate performance */
|
||||
if ((state->dcur.symbol_rate / 1000) <= 5000) {
|
||||
value = 29777 / (state->dcur.symbol_rate / 1000) + 1;
|
||||
if (value % 2 != 0)
|
||||
value++;
|
||||
ds3000_writereg(state, 0xc3, 0x0d);
|
||||
ds3000_writereg(state, 0xc8, value);
|
||||
ds3000_writereg(state, 0xc4, 0x10);
|
||||
ds3000_writereg(state, 0xc7, 0x0e);
|
||||
} else if ((state->dcur.symbol_rate / 1000) <= 10000) {
|
||||
value = 92166 / (state->dcur.symbol_rate / 1000) + 1;
|
||||
if (value % 2 != 0)
|
||||
value++;
|
||||
ds3000_writereg(state, 0xc3, 0x07);
|
||||
ds3000_writereg(state, 0xc8, value);
|
||||
ds3000_writereg(state, 0xc4, 0x09);
|
||||
ds3000_writereg(state, 0xc7, 0x12);
|
||||
} else if ((state->dcur.symbol_rate / 1000) <= 20000) {
|
||||
value = 64516 / (state->dcur.symbol_rate / 1000) + 1;
|
||||
ds3000_writereg(state, 0xc3, value);
|
||||
ds3000_writereg(state, 0xc8, 0x0e);
|
||||
ds3000_writereg(state, 0xc4, 0x07);
|
||||
ds3000_writereg(state, 0xc7, 0x18);
|
||||
} else {
|
||||
value = 129032 / (state->dcur.symbol_rate / 1000) + 1;
|
||||
ds3000_writereg(state, 0xc3, value);
|
||||
ds3000_writereg(state, 0xc8, 0x0a);
|
||||
ds3000_writereg(state, 0xc4, 0x05);
|
||||
ds3000_writereg(state, 0xc7, 0x24);
|
||||
}
|
||||
|
||||
/* normalized symbol rate rounded to the closest integer */
|
||||
value = (((state->dcur.symbol_rate / 1000) << 16) +
|
||||
(DS3000_SAMPLE_RATE / 2)) / DS3000_SAMPLE_RATE;
|
||||
ds3000_writereg(state, 0x61, value & 0x00ff);
|
||||
ds3000_writereg(state, 0x62, (value & 0xff00) >> 8);
|
||||
|
||||
/* co-channel interference cancellation disabled */
|
||||
ds3000_writereg(state, 0x56, 0x00);
|
||||
|
||||
/* equalizer disabled */
|
||||
ds3000_writereg(state, 0x76, 0x00);
|
||||
|
||||
/*ds3000_writereg(state, 0x08, 0x03);
|
||||
ds3000_writereg(state, 0xfd, 0x22);
|
||||
ds3000_writereg(state, 0x08, 0x07);
|
||||
ds3000_writereg(state, 0xfd, 0x42);
|
||||
ds3000_writereg(state, 0x08, 0x07);*/
|
||||
|
||||
if (state->config->ci_mode) {
|
||||
switch (c->delivery_system) {
|
||||
case SYS_DVBS:
|
||||
default:
|
||||
ds3000_writereg(state, 0xfd, 0x80);
|
||||
ds3000_writereg(state, 0xfd, 0x80);
|
||||
break;
|
||||
case SYS_DVBS2:
|
||||
ds3000_writereg(state, 0xfd, 0x01);
|
||||
break;
|
||||
case SYS_DVBS2:
|
||||
ds3000_writereg(state, 0xfd, 0x01);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* ds3000 out of software reset */
|
||||
ds3000_writereg(state, 0x00, 0x00);
|
||||
/* start ds3000 build-in uC */
|
||||
ds3000_writereg(state, 0xb2, 0x00);
|
||||
/* ds3000 out of software reset */
|
||||
ds3000_writereg(state, 0x00, 0x00);
|
||||
/* start ds3000 build-in uC */
|
||||
ds3000_writereg(state, 0xb2, 0x00);
|
||||
|
||||
/* TODO: calculate and set carrier offset */
|
||||
/* TODO: calculate and set carrier offset */
|
||||
|
||||
/* wait before retrying */
|
||||
for (i = 0; i < 30 ; i++) {
|
||||
if (ds3000_is_tuned(fe)) {
|
||||
dprintk("%s: Tuned\n", __func__);
|
||||
ds3000_dump_registers(fe);
|
||||
goto tuned;
|
||||
}
|
||||
msleep(1);
|
||||
}
|
||||
for (i = 0; i < 30 ; i++) {
|
||||
ds3000_read_status(fe, &status);
|
||||
if (status && FE_HAS_LOCK)
|
||||
break;
|
||||
|
||||
dprintk("%s: Not tuned\n", __func__);
|
||||
ds3000_dump_registers(fe);
|
||||
msleep(10);
|
||||
}
|
||||
|
||||
} while (--retune);
|
||||
|
||||
tuned:
|
||||
return ret;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static enum dvbfe_algo ds3000_get_algo(struct dvb_frontend *fe)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user