renegade-project/linux-next
2
0
Fork 0
mirror of https://github.com/edk2-porting/linux-next.git synced 2024-12-19 02:34:01 +08:00
Code

MIPS: traps: 64bit kernels should read CP0_EBase 64bit

Browse Source 
When reading the CP0_EBase register containing the WG (write gate) bit,
the ebase variable should be set to the full value of the register, i.e.
on a 64-bit kernel the full 64-bit width of the register via
read_cp0_ebase_64(), and on a 32-bit kernel the full 32-bit width
including bits 31:30 which may be writeable.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14148/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
James Hogan 2016-09-01 17:30:07 +01:00 committed by Ralf Baechle
parent 72bc8c75ea
commit 18022894ec
1 changed files with 11 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
arch/mips/kernel/traps.c
View File

@ -2215,8 +2215,17 @@ void __init trap_init(void)
} else {
ebase = CAC_BASE;
if (cpu_has_mips_r2_r6)
ebase += (read_c0_ebase() & 0x3ffff000);
if (cpu_has_mips_r2_r6) {
if (cpu_has_ebase_wg) {
#ifdef CONFIG_64BIT
ebase = (read_c0_ebase_64() & ~0xfff);
#else
ebase = (read_c0_ebase() & ~0xfff);
#endif
} else {
ebase += (read_c0_ebase() & 0x3ffff000);
}
}
}
if (cpu_has_mmips) {