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https://github.com/edk2-porting/linux-next.git
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Merge branch 'alx-msix'
Tobias Regnery says: ==================== alx: add msi-x support This patchset adds msi-x support to the alx driver. It is a preparatory series for multi queue support, which I am currently working on. As there is no advantage over msi interrupts without multi queue support, msi-x interrupts are disabled by default. In order to test for regressions, a new module parameter is added to enable msi-x interrupts. Based on information of the downstream driver at github.com/qca/alx ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
171a6c523f
@ -76,11 +76,19 @@ enum alx_device_quirks {
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ALX_DEV_QUIRK_MSI_INTX_DISABLE_BUG = BIT(0),
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};
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#define ALX_FLAG_USING_MSIX BIT(0)
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#define ALX_FLAG_USING_MSI BIT(1)
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struct alx_priv {
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struct net_device *dev;
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struct alx_hw hw;
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/* msi-x vectors */
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int num_vec;
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struct msix_entry *msix_entries;
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char irq_lbl[IFNAMSIZ + 8];
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/* all descriptor memory */
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struct {
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dma_addr_t dma;
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@ -105,7 +113,7 @@ struct alx_priv {
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u16 msg_enable;
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bool msi;
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int flags;
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/* protects hw.stats */
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spinlock_t stats_lock;
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@ -1031,6 +1031,20 @@ void alx_configure_basic(struct alx_hw *hw)
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alx_write_mem32(hw, ALX_WRR, val);
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}
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void alx_mask_msix(struct alx_hw *hw, int index, bool mask)
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{
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u32 reg, val;
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reg = ALX_MSIX_ENTRY_BASE + index * PCI_MSIX_ENTRY_SIZE +
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PCI_MSIX_ENTRY_VECTOR_CTRL;
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val = mask ? PCI_MSIX_ENTRY_CTRL_MASKBIT : 0;
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alx_write_mem32(hw, reg, val);
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alx_post_write(hw);
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}
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bool alx_get_phy_info(struct alx_hw *hw)
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{
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u16 devs1, devs2;
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@ -562,6 +562,7 @@ int alx_reset_mac(struct alx_hw *hw);
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void alx_set_macaddr(struct alx_hw *hw, const u8 *addr);
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bool alx_phy_configured(struct alx_hw *hw);
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void alx_configure_basic(struct alx_hw *hw);
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void alx_mask_msix(struct alx_hw *hw, int index, bool mask);
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void alx_disable_rss(struct alx_hw *hw);
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bool alx_get_phy_info(struct alx_hw *hw);
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void alx_update_hw_stats(struct alx_hw *hw);
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@ -51,6 +51,9 @@
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const char alx_drv_name[] = "alx";
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static bool msix = false;
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module_param(msix, bool, 0);
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MODULE_PARM_DESC(msix, "Enable msi-x interrupt support");
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static void alx_free_txbuf(struct alx_priv *alx, int entry)
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{
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@ -292,32 +295,29 @@ static int alx_poll(struct napi_struct *napi, int budget)
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napi_complete(&alx->napi);
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/* enable interrupt */
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spin_lock_irqsave(&alx->irq_lock, flags);
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alx->int_mask |= ALX_ISR_TX_Q0 | ALX_ISR_RX_Q0;
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alx_write_mem32(hw, ALX_IMR, alx->int_mask);
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spin_unlock_irqrestore(&alx->irq_lock, flags);
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if (alx->flags & ALX_FLAG_USING_MSIX) {
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alx_mask_msix(hw, 1, false);
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} else {
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spin_lock_irqsave(&alx->irq_lock, flags);
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alx->int_mask |= ALX_ISR_TX_Q0 | ALX_ISR_RX_Q0;
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alx_write_mem32(hw, ALX_IMR, alx->int_mask);
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spin_unlock_irqrestore(&alx->irq_lock, flags);
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}
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alx_post_write(hw);
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return work;
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}
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static irqreturn_t alx_intr_handle(struct alx_priv *alx, u32 intr)
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static bool alx_intr_handle_misc(struct alx_priv *alx, u32 intr)
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{
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struct alx_hw *hw = &alx->hw;
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bool write_int_mask = false;
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spin_lock(&alx->irq_lock);
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/* ACK interrupt */
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alx_write_mem32(hw, ALX_ISR, intr | ALX_ISR_DIS);
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intr &= alx->int_mask;
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if (intr & ALX_ISR_FATAL) {
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netif_warn(alx, hw, alx->dev,
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"fatal interrupt 0x%x, resetting\n", intr);
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alx_schedule_reset(alx);
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goto out;
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return true;
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}
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if (intr & ALX_ISR_ALERT)
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@ -329,19 +329,32 @@ static irqreturn_t alx_intr_handle(struct alx_priv *alx, u32 intr)
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* is cleared, the interrupt status could be cleared.
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*/
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alx->int_mask &= ~ALX_ISR_PHY;
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write_int_mask = true;
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alx_write_mem32(hw, ALX_IMR, alx->int_mask);
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alx_schedule_link_check(alx);
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}
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return false;
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}
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static irqreturn_t alx_intr_handle(struct alx_priv *alx, u32 intr)
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{
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struct alx_hw *hw = &alx->hw;
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spin_lock(&alx->irq_lock);
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/* ACK interrupt */
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alx_write_mem32(hw, ALX_ISR, intr | ALX_ISR_DIS);
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intr &= alx->int_mask;
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if (alx_intr_handle_misc(alx, intr))
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goto out;
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if (intr & (ALX_ISR_TX_Q0 | ALX_ISR_RX_Q0)) {
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napi_schedule(&alx->napi);
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/* mask rx/tx interrupt, enable them when napi complete */
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alx->int_mask &= ~ALX_ISR_ALL_QUEUES;
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write_int_mask = true;
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}
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if (write_int_mask)
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alx_write_mem32(hw, ALX_IMR, alx->int_mask);
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}
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alx_write_mem32(hw, ALX_ISR, 0);
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@ -350,6 +363,46 @@ static irqreturn_t alx_intr_handle(struct alx_priv *alx, u32 intr)
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return IRQ_HANDLED;
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}
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static irqreturn_t alx_intr_msix_ring(int irq, void *data)
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{
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struct alx_priv *alx = data;
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struct alx_hw *hw = &alx->hw;
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/* mask interrupt to ACK chip */
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alx_mask_msix(hw, 1, true);
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/* clear interrupt status */
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alx_write_mem32(hw, ALX_ISR, (ALX_ISR_TX_Q0 | ALX_ISR_RX_Q0));
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napi_schedule(&alx->napi);
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return IRQ_HANDLED;
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}
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static irqreturn_t alx_intr_msix_misc(int irq, void *data)
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{
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struct alx_priv *alx = data;
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struct alx_hw *hw = &alx->hw;
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u32 intr;
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/* mask interrupt to ACK chip */
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alx_mask_msix(hw, 0, true);
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/* read interrupt status */
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intr = alx_read_mem32(hw, ALX_ISR);
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intr &= (alx->int_mask & ~ALX_ISR_ALL_QUEUES);
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if (alx_intr_handle_misc(alx, intr))
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return IRQ_HANDLED;
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/* clear interrupt status */
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alx_write_mem32(hw, ALX_ISR, intr);
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/* enable interrupt again */
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alx_mask_msix(hw, 0, false);
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return IRQ_HANDLED;
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}
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static irqreturn_t alx_intr_msi(int irq, void *data)
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{
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struct alx_priv *alx = data;
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@ -614,31 +667,136 @@ static void alx_free_rings(struct alx_priv *alx)
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static void alx_config_vector_mapping(struct alx_priv *alx)
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{
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struct alx_hw *hw = &alx->hw;
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u32 tbl = 0;
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alx_write_mem32(hw, ALX_MSI_MAP_TBL1, 0);
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if (alx->flags & ALX_FLAG_USING_MSIX) {
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tbl |= 1 << ALX_MSI_MAP_TBL1_TXQ0_SHIFT;
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tbl |= 1 << ALX_MSI_MAP_TBL1_RXQ0_SHIFT;
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}
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alx_write_mem32(hw, ALX_MSI_MAP_TBL1, tbl);
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alx_write_mem32(hw, ALX_MSI_MAP_TBL2, 0);
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alx_write_mem32(hw, ALX_MSI_ID_MAP, 0);
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}
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static bool alx_enable_msix(struct alx_priv *alx)
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{
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int i, err, num_vec = 2;
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alx->msix_entries = kcalloc(num_vec, sizeof(struct msix_entry),
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GFP_KERNEL);
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if (!alx->msix_entries) {
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netdev_warn(alx->dev, "Allocation of msix entries failed!\n");
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return false;
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}
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for (i = 0; i < num_vec; i++)
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alx->msix_entries[i].entry = i;
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err = pci_enable_msix(alx->hw.pdev, alx->msix_entries, num_vec);
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if (err) {
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kfree(alx->msix_entries);
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netdev_warn(alx->dev, "Enabling MSI-X interrupts failed!\n");
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return false;
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}
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alx->num_vec = num_vec;
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return true;
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}
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static int alx_request_msix(struct alx_priv *alx)
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{
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struct net_device *netdev = alx->dev;
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int i, err, vector = 0, free_vector = 0;
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err = request_irq(alx->msix_entries[0].vector, alx_intr_msix_misc,
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0, netdev->name, alx);
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if (err)
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goto out_err;
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vector++;
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sprintf(alx->irq_lbl, "%s-TxRx-0", netdev->name);
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err = request_irq(alx->msix_entries[vector].vector,
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alx_intr_msix_ring, 0, alx->irq_lbl, alx);
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if (err)
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goto out_free;
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return 0;
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out_free:
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free_irq(alx->msix_entries[free_vector++].vector, alx);
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vector--;
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for (i = 0; i < vector; i++)
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free_irq(alx->msix_entries[free_vector++].vector, alx);
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out_err:
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return err;
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}
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static void alx_init_intr(struct alx_priv *alx, bool msix)
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{
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if (msix) {
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if (alx_enable_msix(alx))
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alx->flags |= ALX_FLAG_USING_MSIX;
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}
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if (!(alx->flags & ALX_FLAG_USING_MSIX)) {
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alx->num_vec = 1;
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if (!pci_enable_msi(alx->hw.pdev))
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alx->flags |= ALX_FLAG_USING_MSI;
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}
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}
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static void alx_disable_advanced_intr(struct alx_priv *alx)
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{
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if (alx->flags & ALX_FLAG_USING_MSIX) {
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kfree(alx->msix_entries);
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pci_disable_msix(alx->hw.pdev);
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alx->flags &= ~ALX_FLAG_USING_MSIX;
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}
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if (alx->flags & ALX_FLAG_USING_MSI) {
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pci_disable_msi(alx->hw.pdev);
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alx->flags &= ~ALX_FLAG_USING_MSI;
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}
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}
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static void alx_irq_enable(struct alx_priv *alx)
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{
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struct alx_hw *hw = &alx->hw;
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int i;
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/* level-1 interrupt switch */
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alx_write_mem32(hw, ALX_ISR, 0);
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alx_write_mem32(hw, ALX_IMR, alx->int_mask);
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alx_post_write(hw);
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if (alx->flags & ALX_FLAG_USING_MSIX)
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/* enable all msix irqs */
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for (i = 0; i < alx->num_vec; i++)
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alx_mask_msix(hw, i, false);
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}
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static void alx_irq_disable(struct alx_priv *alx)
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{
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struct alx_hw *hw = &alx->hw;
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int i;
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alx_write_mem32(hw, ALX_ISR, ALX_ISR_DIS);
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alx_write_mem32(hw, ALX_IMR, 0);
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alx_post_write(hw);
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synchronize_irq(alx->hw.pdev->irq);
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if (alx->flags & ALX_FLAG_USING_MSIX) {
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for (i = 0; i < alx->num_vec; i++) {
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alx_mask_msix(hw, i, true);
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synchronize_irq(alx->msix_entries[i].vector);
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}
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} else {
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synchronize_irq(alx->hw.pdev->irq);
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}
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}
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static int alx_request_irq(struct alx_priv *alx)
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@ -650,9 +808,18 @@ static int alx_request_irq(struct alx_priv *alx)
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msi_ctrl = (hw->imt >> 1) << ALX_MSI_RETRANS_TM_SHIFT;
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if (!pci_enable_msi(alx->hw.pdev)) {
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alx->msi = true;
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if (alx->flags & ALX_FLAG_USING_MSIX) {
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alx_write_mem32(hw, ALX_MSI_RETRANS_TIMER, msi_ctrl);
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err = alx_request_msix(alx);
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if (!err)
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goto out;
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/* msix request failed, realloc resources */
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alx_disable_advanced_intr(alx);
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alx_init_intr(alx, false);
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}
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if (alx->flags & ALX_FLAG_USING_MSI) {
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alx_write_mem32(hw, ALX_MSI_RETRANS_TIMER,
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msi_ctrl | ALX_MSI_MASK_SEL_LINE);
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err = request_irq(pdev->irq, alx_intr_msi, 0,
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@ -660,6 +827,7 @@ static int alx_request_irq(struct alx_priv *alx)
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if (!err)
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goto out;
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/* fall back to legacy interrupt */
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alx->flags &= ~ALX_FLAG_USING_MSI;
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pci_disable_msi(alx->hw.pdev);
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}
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@ -669,19 +837,25 @@ static int alx_request_irq(struct alx_priv *alx)
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out:
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if (!err)
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alx_config_vector_mapping(alx);
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else
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netdev_err(alx->dev, "IRQ registration failed!\n");
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return err;
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}
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static void alx_free_irq(struct alx_priv *alx)
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{
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struct pci_dev *pdev = alx->hw.pdev;
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int i;
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free_irq(pdev->irq, alx);
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if (alx->msi) {
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pci_disable_msi(alx->hw.pdev);
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alx->msi = false;
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if (alx->flags & ALX_FLAG_USING_MSIX) {
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/* we have only 2 vectors without multi queue support */
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for (i = 0; i < 2; i++)
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free_irq(alx->msix_entries[i].vector, alx);
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} else {
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free_irq(pdev->irq, alx);
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}
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alx_disable_advanced_intr(alx);
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}
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static int alx_identify_hw(struct alx_priv *alx)
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@ -847,6 +1021,8 @@ static int __alx_open(struct alx_priv *alx, bool resume)
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{
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int err;
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alx_init_intr(alx, msix);
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if (!resume)
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netif_carrier_off(alx->dev);
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@ -1236,7 +1412,10 @@ static void alx_poll_controller(struct net_device *netdev)
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{
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struct alx_priv *alx = netdev_priv(netdev);
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if (alx->msi)
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if (alx->flags & ALX_FLAG_USING_MSIX) {
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alx_intr_msix_misc(0, alx);
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alx_intr_msix_ring(0, alx);
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} else if (alx->flags & ALX_FLAG_USING_MSI)
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alx_intr_msi(0, alx);
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else
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alx_intr_legacy(0, alx);
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