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objtool,x86: Simplify register decode
Since the CFI_reg number now matches the instruction encoding order do away with the op_to_cfi_reg[] and use direct assignment. Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Ingo Molnar <mingo@kernel.org> Acked-by: Josh Poimboeuf <jpoimboe@redhat.com> Tested-by: Nick Desaulniers <ndesaulniers@google.com> Link: https://lkml.kernel.org/r/20210211173627.362004522@infradead.org
This commit is contained in:
Peter Zijlstra
Ingo Molnar
parent
ffc7e74f36
commit
16ef7f159c
@ -17,17 +17,6 @@
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#include <objtool/arch.h>
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#include <objtool/warn.h>
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static unsigned char op_to_cfi_reg[][2] = {
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{CFI_AX, CFI_R8},
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{CFI_CX, CFI_R9},
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{CFI_DX, CFI_R10},
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{CFI_BX, CFI_R11},
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{CFI_SP, CFI_R12},
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{CFI_BP, CFI_R13},
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{CFI_SI, CFI_R14},
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{CFI_DI, CFI_R15},
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};
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static int is_x86_64(const struct elf *elf)
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{
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switch (elf->ehdr.e_machine) {
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@ -94,7 +83,7 @@ int arch_decode_instruction(const struct elf *elf, const struct section *sec,
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unsigned char op1, op2,
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rex = 0, rex_b = 0, rex_r = 0, rex_w = 0, rex_x = 0,
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modrm = 0, modrm_mod = 0, modrm_rm = 0, modrm_reg = 0,
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sib = 0;
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sib = 0 /* , sib_scale = 0, sib_index = 0, sib_base = 0 */;
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struct stack_op *op = NULL;
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struct symbol *sym;
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@ -130,23 +119,29 @@ int arch_decode_instruction(const struct elf *elf, const struct section *sec,
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if (insn.modrm.nbytes) {
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modrm = insn.modrm.bytes[0];
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modrm_mod = X86_MODRM_MOD(modrm);
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modrm_reg = X86_MODRM_REG(modrm);
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modrm_rm = X86_MODRM_RM(modrm);
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modrm_reg = X86_MODRM_REG(modrm) + 8*rex_r;
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modrm_rm = X86_MODRM_RM(modrm) + 8*rex_b;
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}
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if (insn.sib.nbytes)
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if (insn.sib.nbytes) {
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sib = insn.sib.bytes[0];
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/*
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sib_scale = X86_SIB_SCALE(sib);
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sib_index = X86_SIB_INDEX(sib) + 8*rex_x;
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sib_base = X86_SIB_BASE(sib) + 8*rex_b;
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*/
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}
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switch (op1) {
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case 0x1:
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case 0x29:
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if (rex_w && !rex_b && modrm_mod == 3 && modrm_rm == 4) {
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if (rex_w && modrm_mod == 3 && modrm_rm == CFI_SP) {
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/* add/sub reg, %rsp */
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ADD_OP(op) {
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op->src.type = OP_SRC_ADD;
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op->src.reg = op_to_cfi_reg[modrm_reg][rex_r];
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op->src.reg = modrm_reg;
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op->dest.type = OP_DEST_REG;
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op->dest.reg = CFI_SP;
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}
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@ -158,7 +153,7 @@ int arch_decode_instruction(const struct elf *elf, const struct section *sec,
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/* push reg */
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ADD_OP(op) {
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op->src.type = OP_SRC_REG;
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op->src.reg = op_to_cfi_reg[op1 & 0x7][rex_b];
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op->src.reg = (op1 & 0x7) + 8*rex_b;
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op->dest.type = OP_DEST_PUSH;
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}
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@ -170,7 +165,7 @@ int arch_decode_instruction(const struct elf *elf, const struct section *sec,
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ADD_OP(op) {
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op->src.type = OP_SRC_POP;
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op->dest.type = OP_DEST_REG;
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op->dest.reg = op_to_cfi_reg[op1 & 0x7][rex_b];
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op->dest.reg = (op1 & 0x7) + 8*rex_b;
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}
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break;
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@ -223,7 +218,7 @@ int arch_decode_instruction(const struct elf *elf, const struct section *sec,
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break;
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case 0x89:
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if (rex_w && !rex_r && modrm_reg == 4) {
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if (rex_w && modrm_reg == CFI_SP) {
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if (modrm_mod == 3) {
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/* mov %rsp, reg */
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@ -231,17 +226,17 @@ int arch_decode_instruction(const struct elf *elf, const struct section *sec,
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op->src.type = OP_SRC_REG;
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op->src.reg = CFI_SP;
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op->dest.type = OP_DEST_REG;
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op->dest.reg = op_to_cfi_reg[modrm_rm][rex_b];
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op->dest.reg = modrm_rm;
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}
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break;
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} else {
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/* skip nontrivial SIB */
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if (modrm_rm == 4 && !(sib == 0x24 && rex_b == rex_x))
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if ((modrm_rm & 7) == 4 && !(sib == 0x24 && rex_b == rex_x))
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break;
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/* skip RIP relative displacement */
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if (modrm_rm == 5 && modrm_mod == 0)
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if ((modrm_rm & 7) == 5 && modrm_mod == 0)
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break;
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/* mov %rsp, disp(%reg) */
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@ -249,7 +244,7 @@ int arch_decode_instruction(const struct elf *elf, const struct section *sec,
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op->src.type = OP_SRC_REG;
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op->src.reg = CFI_SP;
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op->dest.type = OP_DEST_REG_INDIRECT;
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op->dest.reg = op_to_cfi_reg[modrm_rm][rex_b];
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op->dest.reg = modrm_rm;
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op->dest.offset = insn.displacement.value;
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}
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break;
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@ -258,12 +253,12 @@ int arch_decode_instruction(const struct elf *elf, const struct section *sec,
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break;
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}
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if (rex_w && !rex_b && modrm_mod == 3 && modrm_rm == 4) {
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if (rex_w && modrm_mod == 3 && modrm_rm == CFI_SP) {
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/* mov reg, %rsp */
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ADD_OP(op) {
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op->src.type = OP_SRC_REG;
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op->src.reg = op_to_cfi_reg[modrm_reg][rex_r];
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op->src.reg = modrm_reg;
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op->dest.type = OP_DEST_REG;
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op->dest.reg = CFI_SP;
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}
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@ -272,13 +267,12 @@ int arch_decode_instruction(const struct elf *elf, const struct section *sec,
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/* fallthrough */
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case 0x88:
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if (!rex_b &&
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(modrm_mod == 1 || modrm_mod == 2) && modrm_rm == 5) {
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if ((modrm_mod == 1 || modrm_mod == 2) && modrm_rm == CFI_BP) {
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/* mov reg, disp(%rbp) */
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ADD_OP(op) {
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op->src.type = OP_SRC_REG;
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op->src.reg = op_to_cfi_reg[modrm_reg][rex_r];
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op->src.reg = modrm_reg;
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op->dest.type = OP_DEST_REG_INDIRECT;
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op->dest.reg = CFI_BP;
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op->dest.offset = insn.displacement.value;
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@ -286,12 +280,12 @@ int arch_decode_instruction(const struct elf *elf, const struct section *sec,
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break;
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}
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if (rex_w && !rex_b && modrm_rm == 4 && sib == 0x24) {
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if (rex_w && modrm_rm == CFI_SP && sib == 0x24) {
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/* mov reg, disp(%rsp) */
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ADD_OP(op) {
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op->src.type = OP_SRC_REG;
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op->src.reg = op_to_cfi_reg[modrm_reg][rex_r];
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op->src.reg = modrm_reg;
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op->dest.type = OP_DEST_REG_INDIRECT;
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op->dest.reg = CFI_SP;
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op->dest.offset = insn.displacement.value;
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@ -302,7 +296,10 @@ int arch_decode_instruction(const struct elf *elf, const struct section *sec,
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break;
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case 0x8b:
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if (rex_w && !rex_b && modrm_mod == 1 && modrm_rm == 5) {
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if (!rex_w)
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break;
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if (modrm_mod == 1 && modrm_rm == CFI_BP) {
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/* mov disp(%rbp), reg */
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ADD_OP(op) {
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@ -310,11 +307,12 @@ int arch_decode_instruction(const struct elf *elf, const struct section *sec,
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op->src.reg = CFI_BP;
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op->src.offset = insn.displacement.value;
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op->dest.type = OP_DEST_REG;
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op->dest.reg = op_to_cfi_reg[modrm_reg][rex_r];
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op->dest.reg = modrm_reg;
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}
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break;
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}
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} else if (rex_w && !rex_b && sib == 0x24 &&
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modrm_mod != 3 && modrm_rm == 4) {
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if (modrm_mod != 3 && modrm_rm == CFI_SP && sib == 0x24) {
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/* mov disp(%rsp), reg */
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ADD_OP(op) {
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@ -322,8 +320,9 @@ int arch_decode_instruction(const struct elf *elf, const struct section *sec,
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op->src.reg = CFI_SP;
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op->src.offset = insn.displacement.value;
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op->dest.type = OP_DEST_REG;
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op->dest.reg = op_to_cfi_reg[modrm_reg][rex_r];
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op->dest.reg = modrm_reg;
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}
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break;
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}
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break;
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@ -339,11 +338,11 @@ int arch_decode_instruction(const struct elf *elf, const struct section *sec,
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break;
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/* skip nontrivial SIB */
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if (modrm_rm == 4 && !(sib == 0x24 && rex_b == rex_x))
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if ((modrm_rm & 7) == 4 && !(sib == 0x24 && rex_b == rex_x))
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break;
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/* skip RIP relative displacement */
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if (modrm_rm == 5 && modrm_mod == 0)
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if ((modrm_rm & 7) == 5 && modrm_mod == 0)
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break;
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/* lea disp(%src), %dst */
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@ -356,9 +355,9 @@ int arch_decode_instruction(const struct elf *elf, const struct section *sec,
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/* lea disp(%src), %dst */
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op->src.type = OP_SRC_ADD;
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}
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op->src.reg = op_to_cfi_reg[modrm_rm][rex_b];
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op->src.reg = modrm_rm;
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op->dest.type = OP_DEST_REG;
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op->dest.reg = op_to_cfi_reg[modrm_reg][rex_r];
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op->dest.reg = modrm_reg;
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}
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break;
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