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fpga manager: xilinx-spi: fix write_complete timeout handling
If this routine sleeps because it was scheduled out, it might miss DONE going asserted and consider it a timeout. This would potentially make the code return an error even when programming succeeded. Rewrite the loop to always check DONE after checking if timeout expired so this cannot happen anymore. While there, also add error checking for gpiod_get_value(). Also avoid checking the DONE GPIO in two places, which would make the error-checking code duplicated and more annoying. The new loop it written to still guarantee that we apply 8 extra CCLK cycles after DONE has gone asserted, which is required by the hardware. Reported-by: Tom Rix <trix@redhat.com> Reviewed-by: Tom Rix <trix@redhat.com> Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net> Signed-off-by: Moritz Fischer <mdf@kernel.org>
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@ -151,22 +151,29 @@ static int xilinx_spi_write_complete(struct fpga_manager *mgr,
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struct fpga_image_info *info)
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{
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struct xilinx_spi_conf *conf = mgr->priv;
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unsigned long timeout;
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unsigned long timeout = jiffies + usecs_to_jiffies(info->config_complete_timeout_us);
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bool expired = false;
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int done;
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int ret;
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if (gpiod_get_value(conf->done))
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return xilinx_spi_apply_cclk_cycles(conf);
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/*
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* This loop is carefully written such that if the driver is
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* scheduled out for more than 'timeout', we still check for DONE
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* before giving up and we apply 8 extra CCLK cycles in all cases.
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*/
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while (!expired) {
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expired = time_after(jiffies, timeout);
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timeout = jiffies + usecs_to_jiffies(info->config_complete_timeout_us);
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while (time_before(jiffies, timeout)) {
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done = get_done_gpio(mgr);
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if (done < 0)
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return done;
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ret = xilinx_spi_apply_cclk_cycles(conf);
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if (ret)
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return ret;
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if (gpiod_get_value(conf->done))
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return xilinx_spi_apply_cclk_cycles(conf);
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if (done)
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return 0;
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}
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dev_err(&mgr->dev, "Timeout after config data transfer\n");
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