mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-19 10:44:14 +08:00
sh: sh7724: Update FSI/SPU2 clock
When FSI and Network (= NFS file system) were used at the same time, the I/O of FSI was unstable. This patch updates the SPU2 clock (which is used for FSI) to solve this issue. Special thanks to Jeremy. Signed-off-by: Jeremy Baker <Jeremy.Baker@renesas.com> Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
parent
6f26d19fce
commit
16afc9fb02
@ -1105,6 +1105,11 @@ static int __init arch_setup(void)
|
|||||||
gpio_request(GPIO_FN_FSIOBLRCK, NULL);
|
gpio_request(GPIO_FN_FSIOBLRCK, NULL);
|
||||||
gpio_request(GPIO_FN_CLKAUDIOBO, NULL);
|
gpio_request(GPIO_FN_CLKAUDIOBO, NULL);
|
||||||
|
|
||||||
|
/* set SPU2 clock to 83.4 MHz */
|
||||||
|
clk = clk_get(NULL, "spu_clk");
|
||||||
|
clk_set_rate(clk, clk_round_rate(clk, 83333333));
|
||||||
|
clk_put(clk);
|
||||||
|
|
||||||
/* change parent of FSI B */
|
/* change parent of FSI B */
|
||||||
clk = clk_get(NULL, "fsib_clk");
|
clk = clk_get(NULL, "fsib_clk");
|
||||||
clk_register(&fsimckb_clk);
|
clk_register(&fsimckb_clk);
|
||||||
|
@ -586,7 +586,7 @@ arch_initcall(arch_setup);
|
|||||||
static int __init devices_setup(void)
|
static int __init devices_setup(void)
|
||||||
{
|
{
|
||||||
u16 sw = __raw_readw(SW4140); /* select camera, monitor */
|
u16 sw = __raw_readw(SW4140); /* select camera, monitor */
|
||||||
struct clk *fsia_clk;
|
struct clk *clk;
|
||||||
|
|
||||||
/* register board specific self-refresh code */
|
/* register board specific self-refresh code */
|
||||||
sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF,
|
sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF,
|
||||||
@ -755,13 +755,18 @@ static int __init devices_setup(void)
|
|||||||
gpio_request(GPIO_FN_CLKAUDIOBO, NULL);
|
gpio_request(GPIO_FN_CLKAUDIOBO, NULL);
|
||||||
gpio_request(GPIO_FN_FSIIASD, NULL);
|
gpio_request(GPIO_FN_FSIIASD, NULL);
|
||||||
|
|
||||||
|
/* set SPU2 clock to 83.4 MHz */
|
||||||
|
clk = clk_get(NULL, "spu_clk");
|
||||||
|
clk_set_rate(clk, clk_round_rate(clk, 83333333));
|
||||||
|
clk_put(clk);
|
||||||
|
|
||||||
/* change parent of FSI A */
|
/* change parent of FSI A */
|
||||||
fsia_clk = clk_get(NULL, "fsia_clk");
|
clk = clk_get(NULL, "fsia_clk");
|
||||||
clk_register(&fsimcka_clk);
|
clk_register(&fsimcka_clk);
|
||||||
clk_set_parent(fsia_clk, &fsimcka_clk);
|
clk_set_parent(clk, &fsimcka_clk);
|
||||||
clk_set_rate(fsia_clk, 11000);
|
clk_set_rate(clk, 11000);
|
||||||
clk_set_rate(&fsimcka_clk, 11000);
|
clk_set_rate(&fsimcka_clk, 11000);
|
||||||
clk_put(fsia_clk);
|
clk_put(clk);
|
||||||
|
|
||||||
/* SDHI0 connected to cn7 */
|
/* SDHI0 connected to cn7 */
|
||||||
gpio_request(GPIO_FN_SDHI0CD, NULL);
|
gpio_request(GPIO_FN_SDHI0CD, NULL);
|
||||||
|
Loading…
Reference in New Issue
Block a user