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drm/i915/psr: Update PSR2 SU corruption workaround comment

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Turn out it is not a DMC bug it is actually a HW one, so this
workaround will be needed for current gens, lets update the comment
and remove the FIXME.

BSpec: 7723
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190406005112.27205-1-jose.souza@intel.com
This commit is contained in:
José Roberto de Souza 2019-04-05 17:51:09 -07:00
parent de220cc219
commit 15b7dae007
1 changed files with 2 additions and 4 deletions
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6
drivers/gpu/drm/i915/intel_psr.c
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@ -534,10 +534,8 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
val |= EDP_PSR2_TP2_TIME_2500us;
/*
* FIXME: There is probably a issue in DMC firmwares(icl_dmc_ver1_07.bin
* and kbl_dmc_ver1_04.bin at least) that causes PSR2 SU to fail after
* exiting DC6 if EDP_PSR_TP1_TP3_SEL is kept in PSR_CTL, so for now
* lets workaround the issue by cleaning PSR_CTL before enable PSR2.
* PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is
* recommending keep this bit unset while PSR2 is enabled.
*/
I915_WRITE(EDP_PSR_CTL, 0);