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ath5k: write beacon control register twice when resetting tsf
According to the newly-released Atheros HAL code, asserting the TSF reset bit will toggle a hardware internal state, resulting in a spurious reset on the next chip reset. Whenever we force a TSF bit, write the bit twice to clear the internal signal. Signed-off-by: Bob Copeland <me@bobcopeland.com> Acked-by: Nick Kossifidis <mickflemm@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -633,8 +633,20 @@ u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah)
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*/
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void ath5k_hw_reset_tsf(struct ath5k_hw *ah)
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{
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u32 val;
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ATH5K_TRACE(ah->ah_sc);
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AR5K_REG_ENABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_RESET_TSF);
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val = ath5k_hw_reg_read(ah, AR5K_BEACON) | AR5K_BEACON_RESET_TSF;
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/*
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* Each write to the RESET_TSF bit toggles a hardware internal
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* signal to reset TSF, but if left high it will cause a TSF reset
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* on the next chip reset as well. Thus we always write the value
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* twice to clear the signal.
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*/
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ath5k_hw_reg_write(ah, val, AR5K_BEACON);
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ath5k_hw_reg_write(ah, val, AR5K_BEACON);
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}
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/*
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