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Merge branch 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6

Browse Source 
* 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6:
  OMAP2xxx clock: set up clockdomain pointer in struct clk
  OMAP: Fix race condition with autodeps
  omap: McBSP: Fix incorrect receiver stop in omap_mcbsp_stop
  omap: Initialization of SDRC params on Zoom2
  omap: RX-51: Drop I2C-1 speed to 2200
  omap: SDMA: Fixing bug in omap_dma_set_global_params()
  omap: CONFIG_ISP1301_OMAP redefined in Beagle defconfig
This commit is contained in:
Linus Torvalds 2009-10-15 15:09:55 -07:00
commit 13e356c977
7 changed files with 59 additions and 40 deletions
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1
arch/arm/configs/omap3_beagle_defconfig
View File

@ -969,7 +969,6 @@ CONFIG_USB_ETH_RNDIS=y
#
CONFIG_USB_OTG_UTILS=y
# CONFIG_USB_GPIO_VBUS is not set
# CONFIG_ISP1301_OMAP is not set
CONFIG_TWL4030_USB=y
# CONFIG_NOP_USB_XCEIV is not set
CONFIG_MMC=y

2
arch/arm/mach-omap2/board-rx51-peripherals.c
View File

@ -444,7 +444,7 @@ static int __init rx51_i2c_init(void)
rx51_twldata.vaux3 = &rx51_vaux3_cam;
rx51_twldata.vmmc2 = &rx51_vmmc2;
}
omap_register_i2c_bus(1, 2600, rx51_peripherals_i2c_board_info_1,
omap_register_i2c_bus(1, 2200, rx51_peripherals_i2c_board_info_1,
ARRAY_SIZE(rx51_peripherals_i2c_board_info_1));
omap_register_i2c_bus(2, 100, NULL, 0);
omap_register_i2c_bus(3, 400, NULL, 0);

4
arch/arm/mach-omap2/board-zoom2.c
View File

@ -25,6 +25,7 @@
#include <mach/keypad.h>
#include "mmc-twl4030.h"
#include "sdram-micron-mt46h32m32lf-6.h"
/* Zoom2 has Qwerty keyboard*/
static int board_keymap[] = {
@ -213,7 +214,8 @@ static void __init omap_zoom2_init_irq(void)
{
omap_board_config = zoom2_config;
omap_board_config_size = ARRAY_SIZE(zoom2_config);
omap2_init_common_hw(NULL, NULL);
omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
mt46h32m32lf6_sdrc_params);
omap_init_irq();
omap_gpio_init();
}

1
arch/arm/mach-omap2/clock24xx.c
View File

@ -769,6 +769,7 @@ int __init omap2_clk_init(void)
if (c->cpu & cpu_mask) {
clkdev_add(&c->lk);
clk_register(c->lk.clk);
omap2_init_clk_clkdm(c->lk.clk);
}
/* Check the MPU rate set by bootloader */

74
arch/arm/mach-omap2/clockdomain.c
View File

@ -137,6 +137,36 @@ static void _clkdm_del_autodeps(struct clockdomain *clkdm)
}
}
/*
* _omap2_clkdm_set_hwsup - set the hwsup idle transition bit
* @clkdm: struct clockdomain *
* @enable: int 0 to disable, 1 to enable
*
* Internal helper for actually switching the bit that controls hwsup
* idle transitions for clkdm.
*/
static void _omap2_clkdm_set_hwsup(struct clockdomain *clkdm, int enable)
{
u32 v;
if (cpu_is_omap24xx()) {
if (enable)
v = OMAP24XX_CLKSTCTRL_ENABLE_AUTO;
else
v = OMAP24XX_CLKSTCTRL_DISABLE_AUTO;
} else if (cpu_is_omap34xx()) {
if (enable)
v = OMAP34XX_CLKSTCTRL_ENABLE_AUTO;
else
v = OMAP34XX_CLKSTCTRL_DISABLE_AUTO;
} else {
BUG();
}
cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask,
v << __ffs(clkdm->clktrctrl_mask),
clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL);
}
static struct clockdomain *_clkdm_lookup(const char *name)
{
@ -456,8 +486,6 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm)
*/
void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
{
u32 v;
if (!clkdm)
return;
@ -473,18 +501,7 @@ void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
if (atomic_read(&clkdm->usecount) > 0)
_clkdm_add_autodeps(clkdm);
if (cpu_is_omap24xx())
v = OMAP24XX_CLKSTCTRL_ENABLE_AUTO;
else if (cpu_is_omap34xx())
v = OMAP34XX_CLKSTCTRL_ENABLE_AUTO;
else
BUG();
cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask,
v << __ffs(clkdm->clktrctrl_mask),
clkdm->pwrdm.ptr->prcm_offs,
CM_CLKSTCTRL);
_omap2_clkdm_set_hwsup(clkdm, 1);
pwrdm_clkdm_state_switch(clkdm);
}
@ -500,8 +517,6 @@ void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
*/
void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
{
u32 v;
if (!clkdm)
return;
@ -514,16 +529,7 @@ void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
pr_debug("clockdomain: disabling automatic idle transitions for %s\n",
clkdm->name);
if (cpu_is_omap24xx())
v = OMAP24XX_CLKSTCTRL_DISABLE_AUTO;
else if (cpu_is_omap34xx())
v = OMAP34XX_CLKSTCTRL_DISABLE_AUTO;
else
BUG();
cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask,
v << __ffs(clkdm->clktrctrl_mask),
clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL);
_omap2_clkdm_set_hwsup(clkdm, 0);
if (atomic_read(&clkdm->usecount) > 0)
_clkdm_del_autodeps(clkdm);
@ -569,10 +575,14 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
v = omap2_clkdm_clktrctrl_read(clkdm);
if ((cpu_is_omap34xx() && v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ||
(cpu_is_omap24xx() && v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO))
(cpu_is_omap24xx() && v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO)) {
/* Disable HW transitions when we are changing deps */
_omap2_clkdm_set_hwsup(clkdm, 0);
_clkdm_add_autodeps(clkdm);
else
_omap2_clkdm_set_hwsup(clkdm, 1);
} else {
omap2_clkdm_wakeup(clkdm);
}
pwrdm_wait_transition(clkdm->pwrdm.ptr);
pwrdm_clkdm_state_switch(clkdm);
@ -623,10 +633,14 @@ int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
v = omap2_clkdm_clktrctrl_read(clkdm);
if ((cpu_is_omap34xx() && v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ||
(cpu_is_omap24xx() && v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO))
(cpu_is_omap24xx() && v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO)) {
/* Disable HW transitions when we are changing deps */
_omap2_clkdm_set_hwsup(clkdm, 0);
_clkdm_del_autodeps(clkdm);
else
_omap2_clkdm_set_hwsup(clkdm, 1);
} else {
omap2_clkdm_sleep(clkdm);
}
pwrdm_clkdm_state_switch(clkdm);

15
arch/arm/plat-omap/dma.c
View File

@ -829,10 +829,10 @@ EXPORT_SYMBOL(omap_free_dma);
*
* @param arb_rate
* @param max_fifo_depth
* @param tparams - Number of thereads to reserve : DMA_THREAD_RESERVE_NORM
* DMA_THREAD_RESERVE_ONET
* DMA_THREAD_RESERVE_TWOT
* DMA_THREAD_RESERVE_THREET
* @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
* DMA_THREAD_RESERVE_ONET
* DMA_THREAD_RESERVE_TWOT
* DMA_THREAD_RESERVE_THREET
*/
void
omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
@ -844,11 +844,14 @@ omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
return;
}
if (max_fifo_depth == 0)
max_fifo_depth = 1;
if (arb_rate == 0)
arb_rate = 1;
reg = (arb_rate & 0xff) << 16;
reg |= (0xff & max_fifo_depth);
reg = 0xff & max_fifo_depth;
reg |= (0x3 & tparams) << 12;
reg |= (arb_rate & 0xff) << 16;
dma_write(reg, GCR);
}

2
arch/arm/plat-omap/mcbsp.c
View File

@ -595,7 +595,7 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx)
rx &= 1;
if (cpu_is_omap2430() || cpu_is_omap34xx()) {
w = OMAP_MCBSP_READ(io_base, RCCR);
w |= (tx ? RDISABLE : 0);
w |= (rx ? RDISABLE : 0);
OMAP_MCBSP_WRITE(io_base, RCCR, w);
}
w = OMAP_MCBSP_READ(io_base, SPCR1);