mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-19 02:34:01 +08:00
Merge branch 'sh-pfc-for-v4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
This commit is contained in:
Linus Walleij
commit
12597e4539
@ -19,6 +19,7 @@ Required Properties:
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- "renesas,pfc-r8a7791": for R8A7791 (R-Car M2-W) compatible pin-controller.
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- "renesas,pfc-r8a7793": for R8A7793 (R-Car M2-N) compatible pin-controller.
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- "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller.
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- "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller.
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- "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
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- reg: Base address and length of each memory resource used by the pin
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@ -65,6 +65,11 @@ config PINCTRL_PFC_R8A7794
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depends on ARCH_R8A7794
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select PINCTRL_SH_PFC
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config PINCTRL_PFC_R8A7795
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def_bool y
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depends on ARCH_R8A7795
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select PINCTRL_SH_PFC
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config PINCTRL_PFC_SH7203
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def_bool y
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depends on CPU_SUBTYPE_SH7203
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@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o
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obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o
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obj-$(CONFIG_PINCTRL_PFC_R8A7793) += pfc-r8a7791.o
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obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o
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obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o
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obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o
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obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o
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obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o
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@ -489,6 +489,12 @@ static const struct of_device_id sh_pfc_of_table[] = {
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.data = &r8a7794_pinmux_info,
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},
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#endif
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#ifdef CONFIG_PINCTRL_PFC_R8A7795
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{
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.compatible = "renesas,pfc-r8a7795",
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.data = &r8a7795_pinmux_info,
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},
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#endif
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#ifdef CONFIG_PINCTRL_PFC_SH73A0
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{
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.compatible = "renesas,pfc-sh73a0",
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@ -46,7 +46,9 @@ struct sh_pfc {
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unsigned int nr_gpio_pins;
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struct sh_pfc_chip *gpio;
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#ifdef CONFIG_SUPERH
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struct sh_pfc_chip *func;
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#endif
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struct sh_pfc_pinctrl *pinctrl;
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};
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@ -73,6 +75,7 @@ extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
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extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
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extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
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extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
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extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
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extern const struct sh_pfc_soc_info sh7203_pinmux_info;
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extern const struct sh_pfc_soc_info sh7264_pinmux_info;
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extern const struct sh_pfc_soc_info sh7269_pinmux_info;
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@ -219,10 +219,7 @@ static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset)
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return -ENOSYS;
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found:
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if (pfc->num_irqs)
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return pfc->irqs[i];
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else
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return pfc->info->gpio_irq[i].irq;
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return pfc->irqs[i];
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}
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static int gpio_pin_setup(struct sh_pfc_chip *chip)
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@ -261,6 +258,7 @@ static int gpio_pin_setup(struct sh_pfc_chip *chip)
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* Function GPIOs
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*/
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#ifdef CONFIG_SUPERH
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static int gpio_function_request(struct gpio_chip *gc, unsigned offset)
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{
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static bool __print_once;
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@ -286,17 +284,12 @@ static int gpio_function_request(struct gpio_chip *gc, unsigned offset)
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return ret;
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}
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static void gpio_function_free(struct gpio_chip *gc, unsigned offset)
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{
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}
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static int gpio_function_setup(struct sh_pfc_chip *chip)
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{
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struct sh_pfc *pfc = chip->pfc;
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struct gpio_chip *gc = &chip->gpio_chip;
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gc->request = gpio_function_request;
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gc->free = gpio_function_free;
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gc->label = pfc->info->name;
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gc->owner = THIS_MODULE;
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@ -305,6 +298,7 @@ static int gpio_function_setup(struct sh_pfc_chip *chip)
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return 0;
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}
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#endif
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/* -----------------------------------------------------------------------------
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* Register/unregister
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@ -344,7 +338,6 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
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struct sh_pfc_chip *chip;
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phys_addr_t address;
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unsigned int i;
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int ret;
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if (pfc->info->data_regs == NULL)
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return 0;
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@ -367,7 +360,7 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
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return 0;
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/* If we have IRQ resources make sure their number is correct. */
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if (pfc->num_irqs && pfc->num_irqs != pfc->info->gpio_irq_size) {
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if (pfc->num_irqs != pfc->info->gpio_irq_size) {
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dev_err(pfc->dev, "invalid number of IRQ resources\n");
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return -EINVAL;
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}
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@ -379,20 +372,26 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
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pfc->gpio = chip;
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/* Register the GPIO to pin mappings. As pins with GPIO ports must come
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* first in the ranges, skip the pins without GPIO ports by stopping at
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* the first range that contains such a pin.
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if (IS_ENABLED(CONFIG_OF) && pfc->dev->of_node)
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return 0;
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#ifdef CONFIG_SUPERH
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/*
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* Register the GPIO to pin mappings. As pins with GPIO ports
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* must come first in the ranges, skip the pins without GPIO
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* ports by stopping at the first range that contains such a
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* pin.
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*/
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for (i = 0; i < pfc->nr_ranges; ++i) {
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const struct sh_pfc_pin_range *range = &pfc->ranges[i];
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int ret;
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if (range->start >= pfc->nr_gpio_pins)
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break;
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ret = gpiochip_add_pin_range(&chip->gpio_chip,
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dev_name(pfc->dev),
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range->start, range->start,
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range->end - range->start + 1);
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dev_name(pfc->dev), range->start, range->start,
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range->end - range->start + 1);
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if (ret < 0)
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return ret;
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}
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@ -406,6 +405,7 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
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return PTR_ERR(chip);
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pfc->func = chip;
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#endif /* CONFIG_SUPERH */
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return 0;
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}
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@ -413,7 +413,8 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
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int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc)
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{
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gpiochip_remove(&pfc->gpio->gpio_chip);
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#ifdef CONFIG_SUPERH
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gpiochip_remove(&pfc->func->gpio_chip);
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#endif
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return 0;
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}
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@ -2603,64 +2603,64 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
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};
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static const struct pinmux_irq pinmux_irqs[] = {
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PINMUX_IRQ(irq_pin(0), 0),
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PINMUX_IRQ(irq_pin(1), 1),
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PINMUX_IRQ(irq_pin(2), 2),
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PINMUX_IRQ(irq_pin(3), 3),
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PINMUX_IRQ(irq_pin(4), 4),
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PINMUX_IRQ(irq_pin(5), 5),
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PINMUX_IRQ(irq_pin(6), 6),
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PINMUX_IRQ(irq_pin(7), 7),
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PINMUX_IRQ(irq_pin(8), 8),
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PINMUX_IRQ(irq_pin(9), 9),
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PINMUX_IRQ(irq_pin(10), 10),
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PINMUX_IRQ(irq_pin(11), 11),
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PINMUX_IRQ(irq_pin(12), 12),
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PINMUX_IRQ(irq_pin(13), 13),
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PINMUX_IRQ(irq_pin(14), 14),
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PINMUX_IRQ(irq_pin(15), 15),
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PINMUX_IRQ(irq_pin(16), 320),
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PINMUX_IRQ(irq_pin(17), 321),
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PINMUX_IRQ(irq_pin(18), 85),
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PINMUX_IRQ(irq_pin(19), 84),
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PINMUX_IRQ(irq_pin(20), 160),
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PINMUX_IRQ(irq_pin(21), 161),
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PINMUX_IRQ(irq_pin(22), 162),
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PINMUX_IRQ(irq_pin(23), 163),
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PINMUX_IRQ(irq_pin(24), 175),
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PINMUX_IRQ(irq_pin(25), 176),
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PINMUX_IRQ(irq_pin(26), 177),
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PINMUX_IRQ(irq_pin(27), 178),
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PINMUX_IRQ(irq_pin(28), 322),
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PINMUX_IRQ(irq_pin(29), 323),
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PINMUX_IRQ(irq_pin(30), 324),
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PINMUX_IRQ(irq_pin(31), 192),
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PINMUX_IRQ(irq_pin(32), 193),
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PINMUX_IRQ(irq_pin(33), 194),
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PINMUX_IRQ(irq_pin(34), 195),
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PINMUX_IRQ(irq_pin(35), 196),
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PINMUX_IRQ(irq_pin(36), 197),
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PINMUX_IRQ(irq_pin(37), 198),
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PINMUX_IRQ(irq_pin(38), 199),
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PINMUX_IRQ(irq_pin(39), 200),
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PINMUX_IRQ(irq_pin(40), 66),
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PINMUX_IRQ(irq_pin(41), 102),
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PINMUX_IRQ(irq_pin(42), 103),
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PINMUX_IRQ(irq_pin(43), 109),
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PINMUX_IRQ(irq_pin(44), 110),
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PINMUX_IRQ(irq_pin(45), 111),
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PINMUX_IRQ(irq_pin(46), 112),
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PINMUX_IRQ(irq_pin(47), 113),
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PINMUX_IRQ(irq_pin(48), 114),
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PINMUX_IRQ(irq_pin(49), 115),
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PINMUX_IRQ(irq_pin(50), 301),
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PINMUX_IRQ(irq_pin(51), 290),
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PINMUX_IRQ(irq_pin(52), 296),
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PINMUX_IRQ(irq_pin(53), 325),
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PINMUX_IRQ(irq_pin(54), 326),
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PINMUX_IRQ(irq_pin(55), 327),
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PINMUX_IRQ(irq_pin(56), 328),
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PINMUX_IRQ(irq_pin(57), 329),
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PINMUX_IRQ(0), /* IRQ0 */
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PINMUX_IRQ(1), /* IRQ1 */
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PINMUX_IRQ(2), /* IRQ2 */
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PINMUX_IRQ(3), /* IRQ3 */
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PINMUX_IRQ(4), /* IRQ4 */
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PINMUX_IRQ(5), /* IRQ5 */
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PINMUX_IRQ(6), /* IRQ6 */
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PINMUX_IRQ(7), /* IRQ7 */
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PINMUX_IRQ(8), /* IRQ8 */
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PINMUX_IRQ(9), /* IRQ9 */
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PINMUX_IRQ(10), /* IRQ10 */
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PINMUX_IRQ(11), /* IRQ11 */
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PINMUX_IRQ(12), /* IRQ12 */
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PINMUX_IRQ(13), /* IRQ13 */
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PINMUX_IRQ(14), /* IRQ14 */
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PINMUX_IRQ(15), /* IRQ15 */
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PINMUX_IRQ(320), /* IRQ16 */
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PINMUX_IRQ(321), /* IRQ17 */
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PINMUX_IRQ(85), /* IRQ18 */
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PINMUX_IRQ(84), /* IRQ19 */
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PINMUX_IRQ(160), /* IRQ20 */
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PINMUX_IRQ(161), /* IRQ21 */
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PINMUX_IRQ(162), /* IRQ22 */
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PINMUX_IRQ(163), /* IRQ23 */
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PINMUX_IRQ(175), /* IRQ24 */
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PINMUX_IRQ(176), /* IRQ25 */
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PINMUX_IRQ(177), /* IRQ26 */
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PINMUX_IRQ(178), /* IRQ27 */
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PINMUX_IRQ(322), /* IRQ28 */
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PINMUX_IRQ(323), /* IRQ29 */
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PINMUX_IRQ(324), /* IRQ30 */
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PINMUX_IRQ(192), /* IRQ31 */
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PINMUX_IRQ(193), /* IRQ32 */
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PINMUX_IRQ(194), /* IRQ33 */
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PINMUX_IRQ(195), /* IRQ34 */
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PINMUX_IRQ(196), /* IRQ35 */
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PINMUX_IRQ(197), /* IRQ36 */
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PINMUX_IRQ(198), /* IRQ37 */
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PINMUX_IRQ(199), /* IRQ38 */
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PINMUX_IRQ(200), /* IRQ39 */
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PINMUX_IRQ(66), /* IRQ40 */
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PINMUX_IRQ(102), /* IRQ41 */
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PINMUX_IRQ(103), /* IRQ42 */
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PINMUX_IRQ(109), /* IRQ43 */
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PINMUX_IRQ(110), /* IRQ44 */
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PINMUX_IRQ(111), /* IRQ45 */
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PINMUX_IRQ(112), /* IRQ46 */
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PINMUX_IRQ(113), /* IRQ47 */
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PINMUX_IRQ(114), /* IRQ48 */
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PINMUX_IRQ(115), /* IRQ49 */
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PINMUX_IRQ(301), /* IRQ50 */
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PINMUX_IRQ(290), /* IRQ51 */
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PINMUX_IRQ(296), /* IRQ52 */
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PINMUX_IRQ(325), /* IRQ53 */
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PINMUX_IRQ(326), /* IRQ54 */
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PINMUX_IRQ(327), /* IRQ55 */
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PINMUX_IRQ(328), /* IRQ56 */
|
||||
PINMUX_IRQ(329), /* IRQ57 */
|
||||
};
|
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||||
#define PORTCR_PULMD_OFF (0 << 6)
|
||||
|
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@ -3651,38 +3651,38 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
|
||||
};
|
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|
||||
static const struct pinmux_irq pinmux_irqs[] = {
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PINMUX_IRQ(irq_pin(0), 2, 13), /* IRQ0A */
|
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PINMUX_IRQ(irq_pin(1), 20), /* IRQ1A */
|
||||
PINMUX_IRQ(irq_pin(2), 11, 12), /* IRQ2A */
|
||||
PINMUX_IRQ(irq_pin(3), 10, 14), /* IRQ3A */
|
||||
PINMUX_IRQ(irq_pin(4), 15, 172), /* IRQ4A */
|
||||
PINMUX_IRQ(irq_pin(5), 0, 1), /* IRQ5A */
|
||||
PINMUX_IRQ(irq_pin(6), 121, 173), /* IRQ6A */
|
||||
PINMUX_IRQ(irq_pin(7), 120, 209), /* IRQ7A */
|
||||
PINMUX_IRQ(irq_pin(8), 119), /* IRQ8A */
|
||||
PINMUX_IRQ(irq_pin(9), 118, 210), /* IRQ9A */
|
||||
PINMUX_IRQ(irq_pin(10), 19), /* IRQ10A */
|
||||
PINMUX_IRQ(irq_pin(11), 104), /* IRQ11A */
|
||||
PINMUX_IRQ(irq_pin(12), 42, 97), /* IRQ12A */
|
||||
PINMUX_IRQ(irq_pin(13), 64, 98), /* IRQ13A */
|
||||
PINMUX_IRQ(irq_pin(14), 63, 99), /* IRQ14A */
|
||||
PINMUX_IRQ(irq_pin(15), 62, 100), /* IRQ15A */
|
||||
PINMUX_IRQ(irq_pin(16), 68, 211), /* IRQ16A */
|
||||
PINMUX_IRQ(irq_pin(17), 69), /* IRQ17A */
|
||||
PINMUX_IRQ(irq_pin(18), 70), /* IRQ18A */
|
||||
PINMUX_IRQ(irq_pin(19), 71), /* IRQ19A */
|
||||
PINMUX_IRQ(irq_pin(20), 67), /* IRQ20A */
|
||||
PINMUX_IRQ(irq_pin(21), 202), /* IRQ21A */
|
||||
PINMUX_IRQ(irq_pin(22), 95), /* IRQ22A */
|
||||
PINMUX_IRQ(irq_pin(23), 96), /* IRQ23A */
|
||||
PINMUX_IRQ(irq_pin(24), 180), /* IRQ24A */
|
||||
PINMUX_IRQ(irq_pin(25), 38), /* IRQ25A */
|
||||
PINMUX_IRQ(irq_pin(26), 58, 81), /* IRQ26A */
|
||||
PINMUX_IRQ(irq_pin(27), 57, 168), /* IRQ27A */
|
||||
PINMUX_IRQ(irq_pin(28), 56, 169), /* IRQ28A */
|
||||
PINMUX_IRQ(irq_pin(29), 50, 170), /* IRQ29A */
|
||||
PINMUX_IRQ(irq_pin(30), 49, 171), /* IRQ30A */
|
||||
PINMUX_IRQ(irq_pin(31), 41, 167), /* IRQ31A */
|
||||
PINMUX_IRQ(2, 13), /* IRQ0A */
|
||||
PINMUX_IRQ(20), /* IRQ1A */
|
||||
PINMUX_IRQ(11, 12), /* IRQ2A */
|
||||
PINMUX_IRQ(10, 14), /* IRQ3A */
|
||||
PINMUX_IRQ(15, 172), /* IRQ4A */
|
||||
PINMUX_IRQ(0, 1), /* IRQ5A */
|
||||
PINMUX_IRQ(121, 173), /* IRQ6A */
|
||||
PINMUX_IRQ(120, 209), /* IRQ7A */
|
||||
PINMUX_IRQ(119), /* IRQ8A */
|
||||
PINMUX_IRQ(118, 210), /* IRQ9A */
|
||||
PINMUX_IRQ(19), /* IRQ10A */
|
||||
PINMUX_IRQ(104), /* IRQ11A */
|
||||
PINMUX_IRQ(42, 97), /* IRQ12A */
|
||||
PINMUX_IRQ(64, 98), /* IRQ13A */
|
||||
PINMUX_IRQ(63, 99), /* IRQ14A */
|
||||
PINMUX_IRQ(62, 100), /* IRQ15A */
|
||||
PINMUX_IRQ(68, 211), /* IRQ16A */
|
||||
PINMUX_IRQ(69), /* IRQ17A */
|
||||
PINMUX_IRQ(70), /* IRQ18A */
|
||||
PINMUX_IRQ(71), /* IRQ19A */
|
||||
PINMUX_IRQ(67), /* IRQ20A */
|
||||
PINMUX_IRQ(202), /* IRQ21A */
|
||||
PINMUX_IRQ(95), /* IRQ22A */
|
||||
PINMUX_IRQ(96), /* IRQ23A */
|
||||
PINMUX_IRQ(180), /* IRQ24A */
|
||||
PINMUX_IRQ(38), /* IRQ25A */
|
||||
PINMUX_IRQ(58, 81), /* IRQ26A */
|
||||
PINMUX_IRQ(57, 168), /* IRQ27A */
|
||||
PINMUX_IRQ(56, 169), /* IRQ28A */
|
||||
PINMUX_IRQ(50, 170), /* IRQ29A */
|
||||
PINMUX_IRQ(49, 171), /* IRQ30A */
|
||||
PINMUX_IRQ(41, 167), /* IRQ31A */
|
||||
};
|
||||
|
||||
#define PORTnCR_PULMD_OFF (0 << 6)
|
||||
|
||||
@ -620,18 +620,18 @@ static const u16 pinmux_data[] = {
|
||||
PINMUX_DATA(USB_PENC1_MARK, FN_USB_PENC1),
|
||||
|
||||
PINMUX_IPSR_DATA(IP0_2_0, USB_PENC2),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCK0, SEL_SCIF0_0),
|
||||
PINMUX_IPSR_MSEL(IP0_2_0, SCK0, SEL_SCIF0_0),
|
||||
PINMUX_IPSR_DATA(IP0_2_0, PWM1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP0_2_0, PWMFSW0, SEL_PWMFSW_0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCIF_CLK, SEL_SCIF_0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP0_2_0, TCLK0_C, SEL_TMU0_2),
|
||||
PINMUX_IPSR_MSEL(IP0_2_0, PWMFSW0, SEL_PWMFSW_0),
|
||||
PINMUX_IPSR_MSEL(IP0_2_0, SCIF_CLK, SEL_SCIF_0),
|
||||
PINMUX_IPSR_MSEL(IP0_2_0, TCLK0_C, SEL_TMU0_2),
|
||||
PINMUX_IPSR_DATA(IP0_5_3, BS),
|
||||
PINMUX_IPSR_DATA(IP0_5_3, SD1_DAT2),
|
||||
PINMUX_IPSR_DATA(IP0_5_3, MMC0_D2),
|
||||
PINMUX_IPSR_DATA(IP0_5_3, FD2),
|
||||
PINMUX_IPSR_DATA(IP0_5_3, ATADIR0),
|
||||
PINMUX_IPSR_DATA(IP0_5_3, SDSELF),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP0_5_3, HCTS1, SEL_HSCIF1_0),
|
||||
PINMUX_IPSR_MSEL(IP0_5_3, HCTS1, SEL_HSCIF1_0),
|
||||
PINMUX_IPSR_DATA(IP0_5_3, TX4_C),
|
||||
PINMUX_IPSR_DATA(IP0_7_6, A0),
|
||||
PINMUX_IPSR_DATA(IP0_7_6, SD1_DAT3),
|
||||
@ -641,37 +641,37 @@ static const u16 pinmux_data[] = {
|
||||
PINMUX_IPSR_DATA(IP0_9_8, TX5_D),
|
||||
PINMUX_IPSR_DATA(IP0_9_8, HSPI_TX2_B),
|
||||
PINMUX_IPSR_DATA(IP0_11_10, A21),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP0_11_10, SCK5_D, SEL_SCIF5_3),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP0_11_10, HSPI_CLK2_B, SEL_HSPI2_1),
|
||||
PINMUX_IPSR_MSEL(IP0_11_10, SCK5_D, SEL_SCIF5_3),
|
||||
PINMUX_IPSR_MSEL(IP0_11_10, HSPI_CLK2_B, SEL_HSPI2_1),
|
||||
PINMUX_IPSR_DATA(IP0_13_12, A22),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP0_13_12, RX5_D, SEL_SCIF5_3),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP0_13_12, HSPI_RX2_B, SEL_HSPI2_1),
|
||||
PINMUX_IPSR_MSEL(IP0_13_12, RX5_D, SEL_SCIF5_3),
|
||||
PINMUX_IPSR_MSEL(IP0_13_12, HSPI_RX2_B, SEL_HSPI2_1),
|
||||
PINMUX_IPSR_DATA(IP0_13_12, VI1_R0),
|
||||
PINMUX_IPSR_DATA(IP0_15_14, A23),
|
||||
PINMUX_IPSR_DATA(IP0_15_14, FCLE),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP0_15_14, HSPI_CLK2, SEL_HSPI2_0),
|
||||
PINMUX_IPSR_MSEL(IP0_15_14, HSPI_CLK2, SEL_HSPI2_0),
|
||||
PINMUX_IPSR_DATA(IP0_15_14, VI1_R1),
|
||||
PINMUX_IPSR_DATA(IP0_18_16, A24),
|
||||
PINMUX_IPSR_DATA(IP0_18_16, SD1_CD),
|
||||
PINMUX_IPSR_DATA(IP0_18_16, MMC0_D4),
|
||||
PINMUX_IPSR_DATA(IP0_18_16, FD4),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP0_18_16, HSPI_CS2, SEL_HSPI2_0),
|
||||
PINMUX_IPSR_MSEL(IP0_18_16, HSPI_CS2, SEL_HSPI2_0),
|
||||
PINMUX_IPSR_DATA(IP0_18_16, VI1_R2),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP0_18_16, SSI_WS78_B, SEL_SSI7_1),
|
||||
PINMUX_IPSR_MSEL(IP0_18_16, SSI_WS78_B, SEL_SSI7_1),
|
||||
PINMUX_IPSR_DATA(IP0_22_19, A25),
|
||||
PINMUX_IPSR_DATA(IP0_22_19, SD1_WP),
|
||||
PINMUX_IPSR_DATA(IP0_22_19, MMC0_D5),
|
||||
PINMUX_IPSR_DATA(IP0_22_19, FD5),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP0_22_19, HSPI_RX2, SEL_HSPI2_0),
|
||||
PINMUX_IPSR_MSEL(IP0_22_19, HSPI_RX2, SEL_HSPI2_0),
|
||||
PINMUX_IPSR_DATA(IP0_22_19, VI1_R3),
|
||||
PINMUX_IPSR_DATA(IP0_22_19, TX5_B),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP0_22_19, SSI_SDATA7_B, SEL_SSI7_1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP0_22_19, CTS0_B, SEL_SCIF0_1),
|
||||
PINMUX_IPSR_MSEL(IP0_22_19, SSI_SDATA7_B, SEL_SSI7_1),
|
||||
PINMUX_IPSR_MSEL(IP0_22_19, CTS0_B, SEL_SCIF0_1),
|
||||
PINMUX_IPSR_DATA(IP0_24_23, CLKOUT),
|
||||
PINMUX_IPSR_DATA(IP0_24_23, TX3C_IRDA_TX_C),
|
||||
PINMUX_IPSR_DATA(IP0_24_23, PWM0_B),
|
||||
PINMUX_IPSR_DATA(IP0_25, CS0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP0_25, HSPI_CS2_B, SEL_HSPI2_1),
|
||||
PINMUX_IPSR_MSEL(IP0_25, HSPI_CS2_B, SEL_HSPI2_1),
|
||||
PINMUX_IPSR_DATA(IP0_27_26, CS1_A26),
|
||||
PINMUX_IPSR_DATA(IP0_27_26, HSPI_TX2),
|
||||
PINMUX_IPSR_DATA(IP0_27_26, SDSELF_B),
|
||||
@ -679,11 +679,11 @@ static const u16 pinmux_data[] = {
|
||||
PINMUX_IPSR_DATA(IP0_30_28, FWE),
|
||||
PINMUX_IPSR_DATA(IP0_30_28, ATAG0),
|
||||
PINMUX_IPSR_DATA(IP0_30_28, VI1_R7),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP0_30_28, HRTS1, SEL_HSCIF1_0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP0_30_28, RX4_C, SEL_SCIF4_2),
|
||||
PINMUX_IPSR_MSEL(IP0_30_28, HRTS1, SEL_HSCIF1_0),
|
||||
PINMUX_IPSR_MSEL(IP0_30_28, RX4_C, SEL_SCIF4_2),
|
||||
|
||||
PINMUX_IPSR_DATA(IP1_1_0, EX_CS0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP1_1_0, RX3_C_IRDA_RX_C, SEL_SCIF3_2),
|
||||
PINMUX_IPSR_MSEL(IP1_1_0, RX3_C_IRDA_RX_C, SEL_SCIF3_2),
|
||||
PINMUX_IPSR_DATA(IP1_1_0, MMC0_D6),
|
||||
PINMUX_IPSR_DATA(IP1_1_0, FD6),
|
||||
PINMUX_IPSR_DATA(IP1_3_2, EX_CS1),
|
||||
@ -700,45 +700,45 @@ static const u16 pinmux_data[] = {
|
||||
PINMUX_IPSR_DATA(IP1_10_7, FRE),
|
||||
PINMUX_IPSR_DATA(IP1_10_7, ATACS10),
|
||||
PINMUX_IPSR_DATA(IP1_10_7, VI1_R4),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP1_10_7, RX5_B, SEL_SCIF5_1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP1_10_7, HSCK1, SEL_HSCIF1_0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP1_10_7, SSI_SDATA8_B, SEL_SSI8_1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP1_10_7, RTS0_B_TANS_B, SEL_SCIF0_1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP1_10_7, SSI_SDATA9, SEL_SSI9_0),
|
||||
PINMUX_IPSR_MSEL(IP1_10_7, RX5_B, SEL_SCIF5_1),
|
||||
PINMUX_IPSR_MSEL(IP1_10_7, HSCK1, SEL_HSCIF1_0),
|
||||
PINMUX_IPSR_MSEL(IP1_10_7, SSI_SDATA8_B, SEL_SSI8_1),
|
||||
PINMUX_IPSR_MSEL(IP1_10_7, RTS0_B_TANS_B, SEL_SCIF0_1),
|
||||
PINMUX_IPSR_MSEL(IP1_10_7, SSI_SDATA9, SEL_SSI9_0),
|
||||
PINMUX_IPSR_DATA(IP1_14_11, EX_CS4),
|
||||
PINMUX_IPSR_DATA(IP1_14_11, SD1_DAT0),
|
||||
PINMUX_IPSR_DATA(IP1_14_11, MMC0_D0),
|
||||
PINMUX_IPSR_DATA(IP1_14_11, FD0),
|
||||
PINMUX_IPSR_DATA(IP1_14_11, ATARD0),
|
||||
PINMUX_IPSR_DATA(IP1_14_11, VI1_R5),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP1_14_11, SCK5_B, SEL_SCIF5_1),
|
||||
PINMUX_IPSR_MSEL(IP1_14_11, SCK5_B, SEL_SCIF5_1),
|
||||
PINMUX_IPSR_DATA(IP1_14_11, HTX1),
|
||||
PINMUX_IPSR_DATA(IP1_14_11, TX2_E),
|
||||
PINMUX_IPSR_DATA(IP1_14_11, TX0_B),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP1_14_11, SSI_SCK9, SEL_SSI9_0),
|
||||
PINMUX_IPSR_MSEL(IP1_14_11, SSI_SCK9, SEL_SSI9_0),
|
||||
PINMUX_IPSR_DATA(IP1_18_15, EX_CS5),
|
||||
PINMUX_IPSR_DATA(IP1_18_15, SD1_DAT1),
|
||||
PINMUX_IPSR_DATA(IP1_18_15, MMC0_D1),
|
||||
PINMUX_IPSR_DATA(IP1_18_15, FD1),
|
||||
PINMUX_IPSR_DATA(IP1_18_15, ATAWR0),
|
||||
PINMUX_IPSR_DATA(IP1_18_15, VI1_R6),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP1_18_15, HRX1, SEL_HSCIF1_0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP1_18_15, RX2_E, SEL_SCIF2_4),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP1_18_15, RX0_B, SEL_SCIF0_1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP1_18_15, SSI_WS9, SEL_SSI9_0),
|
||||
PINMUX_IPSR_MSEL(IP1_18_15, HRX1, SEL_HSCIF1_0),
|
||||
PINMUX_IPSR_MSEL(IP1_18_15, RX2_E, SEL_SCIF2_4),
|
||||
PINMUX_IPSR_MSEL(IP1_18_15, RX0_B, SEL_SCIF0_1),
|
||||
PINMUX_IPSR_MSEL(IP1_18_15, SSI_WS9, SEL_SSI9_0),
|
||||
PINMUX_IPSR_DATA(IP1_20_19, MLB_CLK),
|
||||
PINMUX_IPSR_DATA(IP1_20_19, PWM2),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP1_20_19, SCK4, SEL_SCIF4_0),
|
||||
PINMUX_IPSR_MSEL(IP1_20_19, SCK4, SEL_SCIF4_0),
|
||||
PINMUX_IPSR_DATA(IP1_22_21, MLB_SIG),
|
||||
PINMUX_IPSR_DATA(IP1_22_21, PWM3),
|
||||
PINMUX_IPSR_DATA(IP1_22_21, TX4),
|
||||
PINMUX_IPSR_DATA(IP1_24_23, MLB_DAT),
|
||||
PINMUX_IPSR_DATA(IP1_24_23, PWM4),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP1_24_23, RX4, SEL_SCIF4_0),
|
||||
PINMUX_IPSR_MSEL(IP1_24_23, RX4, SEL_SCIF4_0),
|
||||
PINMUX_IPSR_DATA(IP1_28_25, HTX0),
|
||||
PINMUX_IPSR_DATA(IP1_28_25, TX1),
|
||||
PINMUX_IPSR_DATA(IP1_28_25, SDATA),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP1_28_25, CTS0_C, SEL_SCIF0_2),
|
||||
PINMUX_IPSR_MSEL(IP1_28_25, CTS0_C, SEL_SCIF0_2),
|
||||
PINMUX_IPSR_DATA(IP1_28_25, SUB_TCK),
|
||||
PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE2),
|
||||
PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE10),
|
||||
@ -746,39 +746,39 @@ static const u16 pinmux_data[] = {
|
||||
PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE26),
|
||||
PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE34),
|
||||
|
||||
PINMUX_IPSR_MODSEL_DATA(IP2_3_0, HRX0, SEL_HSCIF0_0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP2_3_0, RX1, SEL_SCIF1_0),
|
||||
PINMUX_IPSR_MSEL(IP2_3_0, HRX0, SEL_HSCIF0_0),
|
||||
PINMUX_IPSR_MSEL(IP2_3_0, RX1, SEL_SCIF1_0),
|
||||
PINMUX_IPSR_DATA(IP2_3_0, SCKZ),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP2_3_0, RTS0_C_TANS_C, SEL_SCIF0_2),
|
||||
PINMUX_IPSR_MSEL(IP2_3_0, RTS0_C_TANS_C, SEL_SCIF0_2),
|
||||
PINMUX_IPSR_DATA(IP2_3_0, SUB_TDI),
|
||||
PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE3),
|
||||
PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE11),
|
||||
PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE19),
|
||||
PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE27),
|
||||
PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE35),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP2_7_4, HSCK0, SEL_HSCIF0_0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SCK1, SEL_SCIF1_0),
|
||||
PINMUX_IPSR_MSEL(IP2_7_4, HSCK0, SEL_HSCIF0_0),
|
||||
PINMUX_IPSR_MSEL(IP2_7_4, SCK1, SEL_SCIF1_0),
|
||||
PINMUX_IPSR_DATA(IP2_7_4, MTS),
|
||||
PINMUX_IPSR_DATA(IP2_7_4, PWM5),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SCK0_C, SEL_SCIF0_2),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SSI_SDATA9_B, SEL_SSI9_1),
|
||||
PINMUX_IPSR_MSEL(IP2_7_4, SCK0_C, SEL_SCIF0_2),
|
||||
PINMUX_IPSR_MSEL(IP2_7_4, SSI_SDATA9_B, SEL_SSI9_1),
|
||||
PINMUX_IPSR_DATA(IP2_7_4, SUB_TDO),
|
||||
PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE0),
|
||||
PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE8),
|
||||
PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE16),
|
||||
PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE24),
|
||||
PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE32),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP2_11_8, HCTS0, SEL_HSCIF0_0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP2_11_8, CTS1, SEL_SCIF1_0),
|
||||
PINMUX_IPSR_MSEL(IP2_11_8, HCTS0, SEL_HSCIF0_0),
|
||||
PINMUX_IPSR_MSEL(IP2_11_8, CTS1, SEL_SCIF1_0),
|
||||
PINMUX_IPSR_DATA(IP2_11_8, STM),
|
||||
PINMUX_IPSR_DATA(IP2_11_8, PWM0_D),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP2_11_8, RX0_C, SEL_SCIF0_2),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP2_11_8, SCIF_CLK_C, SEL_SCIF_2),
|
||||
PINMUX_IPSR_MSEL(IP2_11_8, RX0_C, SEL_SCIF0_2),
|
||||
PINMUX_IPSR_MSEL(IP2_11_8, SCIF_CLK_C, SEL_SCIF_2),
|
||||
PINMUX_IPSR_DATA(IP2_11_8, SUB_TRST),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP2_11_8, TCLK1_B, SEL_TMU1_1),
|
||||
PINMUX_IPSR_MSEL(IP2_11_8, TCLK1_B, SEL_TMU1_1),
|
||||
PINMUX_IPSR_DATA(IP2_11_8, CC5_OSCOUT),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP2_15_12, HRTS0, SEL_HSCIF0_0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP2_15_12, RTS1_TANS, SEL_SCIF1_0),
|
||||
PINMUX_IPSR_MSEL(IP2_15_12, HRTS0, SEL_HSCIF0_0),
|
||||
PINMUX_IPSR_MSEL(IP2_15_12, RTS1_TANS, SEL_SCIF1_0),
|
||||
PINMUX_IPSR_DATA(IP2_15_12, MDATA),
|
||||
PINMUX_IPSR_DATA(IP2_15_12, TX0_C),
|
||||
PINMUX_IPSR_DATA(IP2_15_12, SUB_TMS),
|
||||
@ -789,17 +789,17 @@ static const u16 pinmux_data[] = {
|
||||
PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE33),
|
||||
PINMUX_IPSR_DATA(IP2_18_16, DU0_DR0),
|
||||
PINMUX_IPSR_DATA(IP2_18_16, LCDOUT0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP2_18_16, DREQ0, SEL_EXBUS0_0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP2_18_16, GPS_CLK_B, SEL_GPS_1),
|
||||
PINMUX_IPSR_MSEL(IP2_18_16, DREQ0, SEL_EXBUS0_0),
|
||||
PINMUX_IPSR_MSEL(IP2_18_16, GPS_CLK_B, SEL_GPS_1),
|
||||
PINMUX_IPSR_DATA(IP2_18_16, AUDATA0),
|
||||
PINMUX_IPSR_DATA(IP2_18_16, TX5_C),
|
||||
PINMUX_IPSR_DATA(IP2_21_19, DU0_DR1),
|
||||
PINMUX_IPSR_DATA(IP2_21_19, LCDOUT1),
|
||||
PINMUX_IPSR_DATA(IP2_21_19, DACK0),
|
||||
PINMUX_IPSR_DATA(IP2_21_19, DRACK0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP2_21_19, GPS_SIGN_B, SEL_GPS_1),
|
||||
PINMUX_IPSR_MSEL(IP2_21_19, GPS_SIGN_B, SEL_GPS_1),
|
||||
PINMUX_IPSR_DATA(IP2_21_19, AUDATA1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP2_21_19, RX5_C, SEL_SCIF5_2),
|
||||
PINMUX_IPSR_MSEL(IP2_21_19, RX5_C, SEL_SCIF5_2),
|
||||
PINMUX_IPSR_DATA(IP2_22, DU0_DR2),
|
||||
PINMUX_IPSR_DATA(IP2_22, LCDOUT2),
|
||||
PINMUX_IPSR_DATA(IP2_23, DU0_DR3),
|
||||
@ -814,14 +814,14 @@ static const u16 pinmux_data[] = {
|
||||
PINMUX_IPSR_DATA(IP2_27, LCDOUT7),
|
||||
PINMUX_IPSR_DATA(IP2_30_28, DU0_DG0),
|
||||
PINMUX_IPSR_DATA(IP2_30_28, LCDOUT8),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP2_30_28, DREQ1, SEL_EXBUS1_0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP2_30_28, SCL2, SEL_I2C2_0),
|
||||
PINMUX_IPSR_MSEL(IP2_30_28, DREQ1, SEL_EXBUS1_0),
|
||||
PINMUX_IPSR_MSEL(IP2_30_28, SCL2, SEL_I2C2_0),
|
||||
PINMUX_IPSR_DATA(IP2_30_28, AUDATA2),
|
||||
|
||||
PINMUX_IPSR_DATA(IP3_2_0, DU0_DG1),
|
||||
PINMUX_IPSR_DATA(IP3_2_0, LCDOUT9),
|
||||
PINMUX_IPSR_DATA(IP3_2_0, DACK1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP3_2_0, SDA2, SEL_I2C2_0),
|
||||
PINMUX_IPSR_MSEL(IP3_2_0, SDA2, SEL_I2C2_0),
|
||||
PINMUX_IPSR_DATA(IP3_2_0, AUDATA3),
|
||||
PINMUX_IPSR_DATA(IP3_3, DU0_DG2),
|
||||
PINMUX_IPSR_DATA(IP3_3, LCDOUT10),
|
||||
@ -838,16 +838,16 @@ static const u16 pinmux_data[] = {
|
||||
PINMUX_IPSR_DATA(IP3_11_9, DU0_DB0),
|
||||
PINMUX_IPSR_DATA(IP3_11_9, LCDOUT16),
|
||||
PINMUX_IPSR_DATA(IP3_11_9, EX_WAIT1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP3_11_9, SCL1, SEL_I2C1_0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP3_11_9, TCLK1, SEL_TMU1_0),
|
||||
PINMUX_IPSR_MSEL(IP3_11_9, SCL1, SEL_I2C1_0),
|
||||
PINMUX_IPSR_MSEL(IP3_11_9, TCLK1, SEL_TMU1_0),
|
||||
PINMUX_IPSR_DATA(IP3_11_9, AUDATA4),
|
||||
PINMUX_IPSR_DATA(IP3_14_12, DU0_DB1),
|
||||
PINMUX_IPSR_DATA(IP3_14_12, LCDOUT17),
|
||||
PINMUX_IPSR_DATA(IP3_14_12, EX_WAIT2),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SDA1, SEL_I2C1_0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP3_14_12, GPS_MAG_B, SEL_GPS_1),
|
||||
PINMUX_IPSR_MSEL(IP3_14_12, SDA1, SEL_I2C1_0),
|
||||
PINMUX_IPSR_MSEL(IP3_14_12, GPS_MAG_B, SEL_GPS_1),
|
||||
PINMUX_IPSR_DATA(IP3_14_12, AUDATA5),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SCK5_C, SEL_SCIF5_2),
|
||||
PINMUX_IPSR_MSEL(IP3_14_12, SCK5_C, SEL_SCIF5_2),
|
||||
PINMUX_IPSR_DATA(IP3_15, DU0_DB2),
|
||||
PINMUX_IPSR_DATA(IP3_15, LCDOUT18),
|
||||
PINMUX_IPSR_DATA(IP3_16, DU0_DB3),
|
||||
@ -863,14 +863,14 @@ static const u16 pinmux_data[] = {
|
||||
PINMUX_IPSR_DATA(IP3_22_21, DU0_DOTCLKIN),
|
||||
PINMUX_IPSR_DATA(IP3_22_21, QSTVA_QVS),
|
||||
PINMUX_IPSR_DATA(IP3_22_21, TX3_D_IRDA_TX_D),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP3_22_21, SCL3_B, SEL_I2C3_1),
|
||||
PINMUX_IPSR_MSEL(IP3_22_21, SCL3_B, SEL_I2C3_1),
|
||||
PINMUX_IPSR_DATA(IP3_23, DU0_DOTCLKOUT0),
|
||||
PINMUX_IPSR_DATA(IP3_23, QCLK),
|
||||
PINMUX_IPSR_DATA(IP3_26_24, DU0_DOTCLKOUT1),
|
||||
PINMUX_IPSR_DATA(IP3_26_24, QSTVB_QVE),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP3_26_24, RX3_D_IRDA_RX_D, SEL_SCIF3_3),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SDA3_B, SEL_I2C3_1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SDA2_C, SEL_I2C2_2),
|
||||
PINMUX_IPSR_MSEL(IP3_26_24, RX3_D_IRDA_RX_D, SEL_SCIF3_3),
|
||||
PINMUX_IPSR_MSEL(IP3_26_24, SDA3_B, SEL_I2C3_1),
|
||||
PINMUX_IPSR_MSEL(IP3_26_24, SDA2_C, SEL_I2C2_2),
|
||||
PINMUX_IPSR_DATA(IP3_26_24, DACK0_B),
|
||||
PINMUX_IPSR_DATA(IP3_26_24, DRACK0_B),
|
||||
PINMUX_IPSR_DATA(IP3_27, DU0_EXHSYNC_DU0_HSYNC),
|
||||
@ -881,34 +881,34 @@ static const u16 pinmux_data[] = {
|
||||
PINMUX_IPSR_DATA(IP3_31_29, QCPV_QDE),
|
||||
PINMUX_IPSR_DATA(IP3_31_29, CAN1_TX),
|
||||
PINMUX_IPSR_DATA(IP3_31_29, TX2_C),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP3_31_29, SCL2_C, SEL_I2C2_2),
|
||||
PINMUX_IPSR_MSEL(IP3_31_29, SCL2_C, SEL_I2C2_2),
|
||||
PINMUX_IPSR_DATA(IP3_31_29, REMOCON),
|
||||
|
||||
PINMUX_IPSR_DATA(IP4_1_0, DU0_DISP),
|
||||
PINMUX_IPSR_DATA(IP4_1_0, QPOLA),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP4_1_0, CAN_CLK_C, SEL_CANCLK_2),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCK2_C, SEL_SCIF2_2),
|
||||
PINMUX_IPSR_MSEL(IP4_1_0, CAN_CLK_C, SEL_CANCLK_2),
|
||||
PINMUX_IPSR_MSEL(IP4_1_0, SCK2_C, SEL_SCIF2_2),
|
||||
PINMUX_IPSR_DATA(IP4_4_2, DU0_CDE),
|
||||
PINMUX_IPSR_DATA(IP4_4_2, QPOLB),
|
||||
PINMUX_IPSR_DATA(IP4_4_2, CAN1_RX),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP4_4_2, RX2_C, SEL_SCIF2_2),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP4_4_2, DREQ0_B, SEL_EXBUS0_1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SSI_SCK78_B, SEL_SSI7_1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SCK0_B, SEL_SCIF0_1),
|
||||
PINMUX_IPSR_MSEL(IP4_4_2, RX2_C, SEL_SCIF2_2),
|
||||
PINMUX_IPSR_MSEL(IP4_4_2, DREQ0_B, SEL_EXBUS0_1),
|
||||
PINMUX_IPSR_MSEL(IP4_4_2, SSI_SCK78_B, SEL_SSI7_1),
|
||||
PINMUX_IPSR_MSEL(IP4_4_2, SCK0_B, SEL_SCIF0_1),
|
||||
PINMUX_IPSR_DATA(IP4_7_5, DU1_DR0),
|
||||
PINMUX_IPSR_DATA(IP4_7_5, VI2_DATA0_VI2_B0),
|
||||
PINMUX_IPSR_DATA(IP4_7_5, PWM6),
|
||||
PINMUX_IPSR_DATA(IP4_7_5, SD3_CLK),
|
||||
PINMUX_IPSR_DATA(IP4_7_5, TX3_E_IRDA_TX_E),
|
||||
PINMUX_IPSR_DATA(IP4_7_5, AUDCK),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP4_7_5, PWMFSW0_B, SEL_PWMFSW_1),
|
||||
PINMUX_IPSR_MSEL(IP4_7_5, PWMFSW0_B, SEL_PWMFSW_1),
|
||||
PINMUX_IPSR_DATA(IP4_10_8, DU1_DR1),
|
||||
PINMUX_IPSR_DATA(IP4_10_8, VI2_DATA1_VI2_B1),
|
||||
PINMUX_IPSR_DATA(IP4_10_8, PWM0),
|
||||
PINMUX_IPSR_DATA(IP4_10_8, SD3_CMD),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP4_10_8, RX3_E_IRDA_RX_E, SEL_SCIF3_4),
|
||||
PINMUX_IPSR_MSEL(IP4_10_8, RX3_E_IRDA_RX_E, SEL_SCIF3_4),
|
||||
PINMUX_IPSR_DATA(IP4_10_8, AUDSYNC),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP4_10_8, CTS0_D, SEL_SCIF0_3),
|
||||
PINMUX_IPSR_MSEL(IP4_10_8, CTS0_D, SEL_SCIF0_3),
|
||||
PINMUX_IPSR_DATA(IP4_11, DU1_DR2),
|
||||
PINMUX_IPSR_DATA(IP4_11, VI2_G0),
|
||||
PINMUX_IPSR_DATA(IP4_12, DU1_DR3),
|
||||
@ -923,18 +923,18 @@ static const u16 pinmux_data[] = {
|
||||
PINMUX_IPSR_DATA(IP4_16, VI2_G5),
|
||||
PINMUX_IPSR_DATA(IP4_19_17, DU1_DG0),
|
||||
PINMUX_IPSR_DATA(IP4_19_17, VI2_DATA2_VI2_B2),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP4_19_17, SCL1_B, SEL_I2C1_1),
|
||||
PINMUX_IPSR_MSEL(IP4_19_17, SCL1_B, SEL_I2C1_1),
|
||||
PINMUX_IPSR_DATA(IP4_19_17, SD3_DAT2),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP4_19_17, SCK3_E, SEL_SCIF3_4),
|
||||
PINMUX_IPSR_MSEL(IP4_19_17, SCK3_E, SEL_SCIF3_4),
|
||||
PINMUX_IPSR_DATA(IP4_19_17, AUDATA6),
|
||||
PINMUX_IPSR_DATA(IP4_19_17, TX0_D),
|
||||
PINMUX_IPSR_DATA(IP4_22_20, DU1_DG1),
|
||||
PINMUX_IPSR_DATA(IP4_22_20, VI2_DATA3_VI2_B3),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP4_22_20, SDA1_B, SEL_I2C1_1),
|
||||
PINMUX_IPSR_MSEL(IP4_22_20, SDA1_B, SEL_I2C1_1),
|
||||
PINMUX_IPSR_DATA(IP4_22_20, SD3_DAT3),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP4_22_20, SCK5, SEL_SCIF5_0),
|
||||
PINMUX_IPSR_MSEL(IP4_22_20, SCK5, SEL_SCIF5_0),
|
||||
PINMUX_IPSR_DATA(IP4_22_20, AUDATA7),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP4_22_20, RX0_D, SEL_SCIF0_3),
|
||||
PINMUX_IPSR_MSEL(IP4_22_20, RX0_D, SEL_SCIF0_3),
|
||||
PINMUX_IPSR_DATA(IP4_23, DU1_DG2),
|
||||
PINMUX_IPSR_DATA(IP4_23, VI2_G6),
|
||||
PINMUX_IPSR_DATA(IP4_24, DU1_DG3),
|
||||
@ -949,17 +949,17 @@ static const u16 pinmux_data[] = {
|
||||
PINMUX_IPSR_DATA(IP4_28, VI2_R3),
|
||||
PINMUX_IPSR_DATA(IP4_31_29, DU1_DB0),
|
||||
PINMUX_IPSR_DATA(IP4_31_29, VI2_DATA4_VI2_B4),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP4_31_29, SCL2_B, SEL_I2C2_1),
|
||||
PINMUX_IPSR_MSEL(IP4_31_29, SCL2_B, SEL_I2C2_1),
|
||||
PINMUX_IPSR_DATA(IP4_31_29, SD3_DAT0),
|
||||
PINMUX_IPSR_DATA(IP4_31_29, TX5),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP4_31_29, SCK0_D, SEL_SCIF0_3),
|
||||
PINMUX_IPSR_MSEL(IP4_31_29, SCK0_D, SEL_SCIF0_3),
|
||||
|
||||
PINMUX_IPSR_DATA(IP5_2_0, DU1_DB1),
|
||||
PINMUX_IPSR_DATA(IP5_2_0, VI2_DATA5_VI2_B5),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP5_2_0, SDA2_B, SEL_I2C2_1),
|
||||
PINMUX_IPSR_MSEL(IP5_2_0, SDA2_B, SEL_I2C2_1),
|
||||
PINMUX_IPSR_DATA(IP5_2_0, SD3_DAT1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP5_2_0, RX5, SEL_SCIF5_0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP5_2_0, RTS0_D_TANS_D, SEL_SCIF0_3),
|
||||
PINMUX_IPSR_MSEL(IP5_2_0, RX5, SEL_SCIF5_0),
|
||||
PINMUX_IPSR_MSEL(IP5_2_0, RTS0_D_TANS_D, SEL_SCIF0_3),
|
||||
PINMUX_IPSR_DATA(IP5_3, DU1_DB2),
|
||||
PINMUX_IPSR_DATA(IP5_3, VI2_R4),
|
||||
PINMUX_IPSR_DATA(IP5_4, DU1_DB3),
|
||||
@ -969,16 +969,16 @@ static const u16 pinmux_data[] = {
|
||||
PINMUX_IPSR_DATA(IP5_6, DU1_DB5),
|
||||
PINMUX_IPSR_DATA(IP5_6, VI2_R7),
|
||||
PINMUX_IPSR_DATA(IP5_7, DU1_DB6),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP5_7, SCL2_D, SEL_I2C2_3),
|
||||
PINMUX_IPSR_MSEL(IP5_7, SCL2_D, SEL_I2C2_3),
|
||||
PINMUX_IPSR_DATA(IP5_8, DU1_DB7),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP5_8, SDA2_D, SEL_I2C2_3),
|
||||
PINMUX_IPSR_MSEL(IP5_8, SDA2_D, SEL_I2C2_3),
|
||||
PINMUX_IPSR_DATA(IP5_10_9, DU1_DOTCLKIN),
|
||||
PINMUX_IPSR_DATA(IP5_10_9, VI2_CLKENB),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP5_10_9, HSPI_CS1, SEL_HSPI1_0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP5_10_9, SCL1_D, SEL_I2C1_3),
|
||||
PINMUX_IPSR_MSEL(IP5_10_9, HSPI_CS1, SEL_HSPI1_0),
|
||||
PINMUX_IPSR_MSEL(IP5_10_9, SCL1_D, SEL_I2C1_3),
|
||||
PINMUX_IPSR_DATA(IP5_12_11, DU1_DOTCLKOUT),
|
||||
PINMUX_IPSR_DATA(IP5_12_11, VI2_FIELD),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP5_12_11, SDA1_D, SEL_I2C1_3),
|
||||
PINMUX_IPSR_MSEL(IP5_12_11, SDA1_D, SEL_I2C1_3),
|
||||
PINMUX_IPSR_DATA(IP5_14_13, DU1_EXHSYNC_DU1_HSYNC),
|
||||
PINMUX_IPSR_DATA(IP5_14_13, VI2_HSYNC),
|
||||
PINMUX_IPSR_DATA(IP5_14_13, VI3_HSYNC),
|
||||
@ -995,26 +995,26 @@ static const u16 pinmux_data[] = {
|
||||
PINMUX_IPSR_DATA(IP5_20_17, AUDIO_CLKC),
|
||||
PINMUX_IPSR_DATA(IP5_20_17, TX2_D),
|
||||
PINMUX_IPSR_DATA(IP5_20_17, SPEEDIN),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP5_20_17, GPS_SIGN_D, SEL_GPS_3),
|
||||
PINMUX_IPSR_MSEL(IP5_20_17, GPS_SIGN_D, SEL_GPS_3),
|
||||
PINMUX_IPSR_DATA(IP5_23_21, DU1_DISP),
|
||||
PINMUX_IPSR_DATA(IP5_23_21, VI2_DATA6_VI2_B6),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP5_23_21, TCLK0, SEL_TMU0_0),
|
||||
PINMUX_IPSR_MSEL(IP5_23_21, TCLK0, SEL_TMU0_0),
|
||||
PINMUX_IPSR_DATA(IP5_23_21, QSTVA_B_QVS_B),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP5_23_21, HSPI_CLK1, SEL_HSPI1_0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP5_23_21, SCK2_D, SEL_SCIF2_3),
|
||||
PINMUX_IPSR_MSEL(IP5_23_21, HSPI_CLK1, SEL_HSPI1_0),
|
||||
PINMUX_IPSR_MSEL(IP5_23_21, SCK2_D, SEL_SCIF2_3),
|
||||
PINMUX_IPSR_DATA(IP5_23_21, AUDIO_CLKOUT_B),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP5_23_21, GPS_MAG_D, SEL_GPS_3),
|
||||
PINMUX_IPSR_MSEL(IP5_23_21, GPS_MAG_D, SEL_GPS_3),
|
||||
PINMUX_IPSR_DATA(IP5_27_24, DU1_CDE),
|
||||
PINMUX_IPSR_DATA(IP5_27_24, VI2_DATA7_VI2_B7),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP5_27_24, RX3_B_IRDA_RX_B, SEL_SCIF3_1),
|
||||
PINMUX_IPSR_MSEL(IP5_27_24, RX3_B_IRDA_RX_B, SEL_SCIF3_1),
|
||||
PINMUX_IPSR_DATA(IP5_27_24, SD3_WP),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP5_27_24, HSPI_RX1, SEL_HSPI1_0),
|
||||
PINMUX_IPSR_MSEL(IP5_27_24, HSPI_RX1, SEL_HSPI1_0),
|
||||
PINMUX_IPSR_DATA(IP5_27_24, VI1_FIELD),
|
||||
PINMUX_IPSR_DATA(IP5_27_24, VI3_FIELD),
|
||||
PINMUX_IPSR_DATA(IP5_27_24, AUDIO_CLKOUT),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP5_27_24, RX2_D, SEL_SCIF2_3),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP5_27_24, GPS_CLK_C, SEL_GPS_2),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP5_27_24, GPS_CLK_D, SEL_GPS_3),
|
||||
PINMUX_IPSR_MSEL(IP5_27_24, RX2_D, SEL_SCIF2_3),
|
||||
PINMUX_IPSR_MSEL(IP5_27_24, GPS_CLK_C, SEL_GPS_2),
|
||||
PINMUX_IPSR_MSEL(IP5_27_24, GPS_CLK_D, SEL_GPS_3),
|
||||
PINMUX_IPSR_DATA(IP5_28, AUDIO_CLKA),
|
||||
PINMUX_IPSR_DATA(IP5_28, CAN_TXCLK),
|
||||
PINMUX_IPSR_DATA(IP5_30_29, AUDIO_CLKB),
|
||||
@ -1039,82 +1039,82 @@ static const u16 pinmux_data[] = {
|
||||
PINMUX_IPSR_DATA(IP6_11_9, SSI_SCK34),
|
||||
PINMUX_IPSR_DATA(IP6_11_9, CAN_DEBUGOUT6),
|
||||
PINMUX_IPSR_DATA(IP6_11_9, CAN0_TX_B),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP6_11_9, IERX, SEL_IE_0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP6_11_9, SSI_SCK9_C, SEL_SSI9_2),
|
||||
PINMUX_IPSR_MSEL(IP6_11_9, IERX, SEL_IE_0),
|
||||
PINMUX_IPSR_MSEL(IP6_11_9, SSI_SCK9_C, SEL_SSI9_2),
|
||||
PINMUX_IPSR_DATA(IP6_14_12, SSI_WS34),
|
||||
PINMUX_IPSR_DATA(IP6_14_12, CAN_DEBUGOUT7),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP6_14_12, CAN0_RX_B, SEL_CAN0_1),
|
||||
PINMUX_IPSR_MSEL(IP6_14_12, CAN0_RX_B, SEL_CAN0_1),
|
||||
PINMUX_IPSR_DATA(IP6_14_12, IETX),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP6_14_12, SSI_WS9_C, SEL_SSI9_2),
|
||||
PINMUX_IPSR_MSEL(IP6_14_12, SSI_WS9_C, SEL_SSI9_2),
|
||||
PINMUX_IPSR_DATA(IP6_17_15, SSI_SDATA3),
|
||||
PINMUX_IPSR_DATA(IP6_17_15, PWM0_C),
|
||||
PINMUX_IPSR_DATA(IP6_17_15, CAN_DEBUGOUT8),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP6_17_15, CAN_CLK_B, SEL_CANCLK_1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP6_17_15, IECLK, SEL_IE_0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP6_17_15, SCIF_CLK_B, SEL_SCIF_1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP6_17_15, TCLK0_B, SEL_TMU0_1),
|
||||
PINMUX_IPSR_MSEL(IP6_17_15, CAN_CLK_B, SEL_CANCLK_1),
|
||||
PINMUX_IPSR_MSEL(IP6_17_15, IECLK, SEL_IE_0),
|
||||
PINMUX_IPSR_MSEL(IP6_17_15, SCIF_CLK_B, SEL_SCIF_1),
|
||||
PINMUX_IPSR_MSEL(IP6_17_15, TCLK0_B, SEL_TMU0_1),
|
||||
PINMUX_IPSR_DATA(IP6_19_18, SSI_SDATA4),
|
||||
PINMUX_IPSR_DATA(IP6_19_18, CAN_DEBUGOUT9),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP6_19_18, SSI_SDATA9_C, SEL_SSI9_2),
|
||||
PINMUX_IPSR_MSEL(IP6_19_18, SSI_SDATA9_C, SEL_SSI9_2),
|
||||
PINMUX_IPSR_DATA(IP6_22_20, SSI_SCK5),
|
||||
PINMUX_IPSR_DATA(IP6_22_20, ADICLK),
|
||||
PINMUX_IPSR_DATA(IP6_22_20, CAN_DEBUGOUT10),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK3, SEL_SCIF3_0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TCLK0_D, SEL_TMU0_3),
|
||||
PINMUX_IPSR_MSEL(IP6_22_20, SCK3, SEL_SCIF3_0),
|
||||
PINMUX_IPSR_MSEL(IP6_22_20, TCLK0_D, SEL_TMU0_3),
|
||||
PINMUX_IPSR_DATA(IP6_24_23, SSI_WS5),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP6_24_23, ADICS_SAMP, SEL_ADI_0),
|
||||
PINMUX_IPSR_MSEL(IP6_24_23, ADICS_SAMP, SEL_ADI_0),
|
||||
PINMUX_IPSR_DATA(IP6_24_23, CAN_DEBUGOUT11),
|
||||
PINMUX_IPSR_DATA(IP6_24_23, TX3_IRDA_TX),
|
||||
PINMUX_IPSR_DATA(IP6_26_25, SSI_SDATA5),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP6_26_25, ADIDATA, SEL_ADI_0),
|
||||
PINMUX_IPSR_MSEL(IP6_26_25, ADIDATA, SEL_ADI_0),
|
||||
PINMUX_IPSR_DATA(IP6_26_25, CAN_DEBUGOUT12),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP6_26_25, RX3_IRDA_RX, SEL_SCIF3_0),
|
||||
PINMUX_IPSR_MSEL(IP6_26_25, RX3_IRDA_RX, SEL_SCIF3_0),
|
||||
PINMUX_IPSR_DATA(IP6_30_29, SSI_SCK6),
|
||||
PINMUX_IPSR_DATA(IP6_30_29, ADICHS0),
|
||||
PINMUX_IPSR_DATA(IP6_30_29, CAN0_TX),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP6_30_29, IERX_B, SEL_IE_1),
|
||||
PINMUX_IPSR_MSEL(IP6_30_29, IERX_B, SEL_IE_1),
|
||||
|
||||
PINMUX_IPSR_DATA(IP7_1_0, SSI_WS6),
|
||||
PINMUX_IPSR_DATA(IP7_1_0, ADICHS1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_1_0, CAN0_RX, SEL_CAN0_0),
|
||||
PINMUX_IPSR_MSEL(IP7_1_0, CAN0_RX, SEL_CAN0_0),
|
||||
PINMUX_IPSR_DATA(IP7_1_0, IETX_B),
|
||||
PINMUX_IPSR_DATA(IP7_3_2, SSI_SDATA6),
|
||||
PINMUX_IPSR_DATA(IP7_3_2, ADICHS2),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_3_2, CAN_CLK, SEL_CANCLK_0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_3_2, IECLK_B, SEL_IE_1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_6_4, SSI_SCK78, SEL_SSI7_0),
|
||||
PINMUX_IPSR_MSEL(IP7_3_2, CAN_CLK, SEL_CANCLK_0),
|
||||
PINMUX_IPSR_MSEL(IP7_3_2, IECLK_B, SEL_IE_1),
|
||||
PINMUX_IPSR_MSEL(IP7_6_4, SSI_SCK78, SEL_SSI7_0),
|
||||
PINMUX_IPSR_DATA(IP7_6_4, CAN_DEBUGOUT13),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_6_4, IRQ0_B, SEL_INT0_1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_6_4, SSI_SCK9_B, SEL_SSI9_1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_6_4, HSPI_CLK1_C, SEL_HSPI1_2),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_9_7, SSI_WS78, SEL_SSI7_0),
|
||||
PINMUX_IPSR_MSEL(IP7_6_4, IRQ0_B, SEL_INT0_1),
|
||||
PINMUX_IPSR_MSEL(IP7_6_4, SSI_SCK9_B, SEL_SSI9_1),
|
||||
PINMUX_IPSR_MSEL(IP7_6_4, HSPI_CLK1_C, SEL_HSPI1_2),
|
||||
PINMUX_IPSR_MSEL(IP7_9_7, SSI_WS78, SEL_SSI7_0),
|
||||
PINMUX_IPSR_DATA(IP7_9_7, CAN_DEBUGOUT14),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_9_7, IRQ1_B, SEL_INT1_1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_9_7, SSI_WS9_B, SEL_SSI9_1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_9_7, HSPI_CS1_C, SEL_HSPI1_2),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_12_10, SSI_SDATA7, SEL_SSI7_0),
|
||||
PINMUX_IPSR_MSEL(IP7_9_7, IRQ1_B, SEL_INT1_1),
|
||||
PINMUX_IPSR_MSEL(IP7_9_7, SSI_WS9_B, SEL_SSI9_1),
|
||||
PINMUX_IPSR_MSEL(IP7_9_7, HSPI_CS1_C, SEL_HSPI1_2),
|
||||
PINMUX_IPSR_MSEL(IP7_12_10, SSI_SDATA7, SEL_SSI7_0),
|
||||
PINMUX_IPSR_DATA(IP7_12_10, CAN_DEBUGOUT15),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_12_10, IRQ2_B, SEL_INT2_1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TCLK1_C, SEL_TMU1_2),
|
||||
PINMUX_IPSR_MSEL(IP7_12_10, IRQ2_B, SEL_INT2_1),
|
||||
PINMUX_IPSR_MSEL(IP7_12_10, TCLK1_C, SEL_TMU1_2),
|
||||
PINMUX_IPSR_DATA(IP7_12_10, HSPI_TX1_C),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_14_13, SSI_SDATA8, SEL_SSI8_0),
|
||||
PINMUX_IPSR_MSEL(IP7_14_13, SSI_SDATA8, SEL_SSI8_0),
|
||||
PINMUX_IPSR_DATA(IP7_14_13, VSP),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_14_13, IRQ3_B, SEL_INT3_1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_14_13, HSPI_RX1_C, SEL_HSPI1_2),
|
||||
PINMUX_IPSR_MSEL(IP7_14_13, IRQ3_B, SEL_INT3_1),
|
||||
PINMUX_IPSR_MSEL(IP7_14_13, HSPI_RX1_C, SEL_HSPI1_2),
|
||||
PINMUX_IPSR_DATA(IP7_16_15, SD0_CLK),
|
||||
PINMUX_IPSR_DATA(IP7_16_15, ATACS01),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_16_15, SCK1_B, SEL_SCIF1_1),
|
||||
PINMUX_IPSR_MSEL(IP7_16_15, SCK1_B, SEL_SCIF1_1),
|
||||
PINMUX_IPSR_DATA(IP7_18_17, SD0_CMD),
|
||||
PINMUX_IPSR_DATA(IP7_18_17, ATACS11),
|
||||
PINMUX_IPSR_DATA(IP7_18_17, TX1_B),
|
||||
PINMUX_IPSR_DATA(IP7_18_17, CC5_TDO),
|
||||
PINMUX_IPSR_DATA(IP7_20_19, SD0_DAT0),
|
||||
PINMUX_IPSR_DATA(IP7_20_19, ATADIR1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_20_19, RX1_B, SEL_SCIF1_1),
|
||||
PINMUX_IPSR_MSEL(IP7_20_19, RX1_B, SEL_SCIF1_1),
|
||||
PINMUX_IPSR_DATA(IP7_20_19, CC5_TRST),
|
||||
PINMUX_IPSR_DATA(IP7_22_21, SD0_DAT1),
|
||||
PINMUX_IPSR_DATA(IP7_22_21, ATAG1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_22_21, SCK2_B, SEL_SCIF2_1),
|
||||
PINMUX_IPSR_MSEL(IP7_22_21, SCK2_B, SEL_SCIF2_1),
|
||||
PINMUX_IPSR_DATA(IP7_22_21, CC5_TMS),
|
||||
PINMUX_IPSR_DATA(IP7_24_23, SD0_DAT2),
|
||||
PINMUX_IPSR_DATA(IP7_24_23, ATARD1),
|
||||
@ -1122,17 +1122,17 @@ static const u16 pinmux_data[] = {
|
||||
PINMUX_IPSR_DATA(IP7_24_23, CC5_TCK),
|
||||
PINMUX_IPSR_DATA(IP7_26_25, SD0_DAT3),
|
||||
PINMUX_IPSR_DATA(IP7_26_25, ATAWR1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_26_25, RX2_B, SEL_SCIF2_1),
|
||||
PINMUX_IPSR_MSEL(IP7_26_25, RX2_B, SEL_SCIF2_1),
|
||||
PINMUX_IPSR_DATA(IP7_26_25, CC5_TDI),
|
||||
PINMUX_IPSR_DATA(IP7_28_27, SD0_CD),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_28_27, DREQ2, SEL_EXBUS2_0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_28_27, RTS1_B_TANS_B, SEL_SCIF1_1),
|
||||
PINMUX_IPSR_MSEL(IP7_28_27, DREQ2, SEL_EXBUS2_0),
|
||||
PINMUX_IPSR_MSEL(IP7_28_27, RTS1_B_TANS_B, SEL_SCIF1_1),
|
||||
PINMUX_IPSR_DATA(IP7_30_29, SD0_WP),
|
||||
PINMUX_IPSR_DATA(IP7_30_29, DACK2),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP7_30_29, CTS1_B, SEL_SCIF1_1),
|
||||
PINMUX_IPSR_MSEL(IP7_30_29, CTS1_B, SEL_SCIF1_1),
|
||||
|
||||
PINMUX_IPSR_DATA(IP8_3_0, HSPI_CLK0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP8_3_0, CTS0, SEL_SCIF0_0),
|
||||
PINMUX_IPSR_MSEL(IP8_3_0, CTS0, SEL_SCIF0_0),
|
||||
PINMUX_IPSR_DATA(IP8_3_0, USB_OVC0),
|
||||
PINMUX_IPSR_DATA(IP8_3_0, AD_CLK),
|
||||
PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE4),
|
||||
@ -1141,7 +1141,7 @@ static const u16 pinmux_data[] = {
|
||||
PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE28),
|
||||
PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE36),
|
||||
PINMUX_IPSR_DATA(IP8_7_4, HSPI_CS0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP8_7_4, RTS0_TANS, SEL_SCIF0_0),
|
||||
PINMUX_IPSR_MSEL(IP8_7_4, RTS0_TANS, SEL_SCIF0_0),
|
||||
PINMUX_IPSR_DATA(IP8_7_4, USB_OVC1),
|
||||
PINMUX_IPSR_DATA(IP8_7_4, AD_DI),
|
||||
PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE5),
|
||||
@ -1159,7 +1159,7 @@ static const u16 pinmux_data[] = {
|
||||
PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE30),
|
||||
PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE38),
|
||||
PINMUX_IPSR_DATA(IP8_15_12, HSPI_RX0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP8_15_12, RX0, SEL_SCIF0_0),
|
||||
PINMUX_IPSR_MSEL(IP8_15_12, RX0, SEL_SCIF0_0),
|
||||
PINMUX_IPSR_DATA(IP8_15_12, CAN_STEP0),
|
||||
PINMUX_IPSR_DATA(IP8_15_12, AD_NCS),
|
||||
PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE7),
|
||||
@ -1181,25 +1181,25 @@ static const u16 pinmux_data[] = {
|
||||
PINMUX_IPSR_DATA(IP8_22_21, HTX1_B),
|
||||
PINMUX_IPSR_DATA(IP8_22_21, MT1_SYNC),
|
||||
PINMUX_IPSR_DATA(IP8_24_23, VI0_FIELD),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP8_24_23, RX1_C, SEL_SCIF1_2),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP8_24_23, HRX1_B, SEL_HSCIF1_1),
|
||||
PINMUX_IPSR_MSEL(IP8_24_23, RX1_C, SEL_SCIF1_2),
|
||||
PINMUX_IPSR_MSEL(IP8_24_23, HRX1_B, SEL_HSCIF1_1),
|
||||
PINMUX_IPSR_DATA(IP8_27_25, VI0_HSYNC),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP8_27_25, VI0_DATA0_B_VI0_B0_B, SEL_VI0_1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP8_27_25, CTS1_C, SEL_SCIF1_2),
|
||||
PINMUX_IPSR_MSEL(IP8_27_25, VI0_DATA0_B_VI0_B0_B, SEL_VI0_1),
|
||||
PINMUX_IPSR_MSEL(IP8_27_25, CTS1_C, SEL_SCIF1_2),
|
||||
PINMUX_IPSR_DATA(IP8_27_25, TX4_D),
|
||||
PINMUX_IPSR_DATA(IP8_27_25, MMC1_CMD),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP8_27_25, HSCK1_B, SEL_HSCIF1_1),
|
||||
PINMUX_IPSR_MSEL(IP8_27_25, HSCK1_B, SEL_HSCIF1_1),
|
||||
PINMUX_IPSR_DATA(IP8_30_28, VI0_VSYNC),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP8_30_28, VI0_DATA1_B_VI0_B1_B, SEL_VI0_1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP8_30_28, RTS1_C_TANS_C, SEL_SCIF1_2),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP8_30_28, RX4_D, SEL_SCIF4_3),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP8_30_28, PWMFSW0_C, SEL_PWMFSW_2),
|
||||
PINMUX_IPSR_MSEL(IP8_30_28, VI0_DATA1_B_VI0_B1_B, SEL_VI0_1),
|
||||
PINMUX_IPSR_MSEL(IP8_30_28, RTS1_C_TANS_C, SEL_SCIF1_2),
|
||||
PINMUX_IPSR_MSEL(IP8_30_28, RX4_D, SEL_SCIF4_3),
|
||||
PINMUX_IPSR_MSEL(IP8_30_28, PWMFSW0_C, SEL_PWMFSW_2),
|
||||
|
||||
PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI0_DATA0_VI0_B0, SEL_VI0_0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP9_1_0, HRTS1_B, SEL_HSCIF1_1),
|
||||
PINMUX_IPSR_MSEL(IP9_1_0, VI0_DATA0_VI0_B0, SEL_VI0_0),
|
||||
PINMUX_IPSR_MSEL(IP9_1_0, HRTS1_B, SEL_HSCIF1_1),
|
||||
PINMUX_IPSR_DATA(IP9_1_0, MT1_VCXO),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI0_DATA1_VI0_B1, SEL_VI0_0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP9_3_2, HCTS1_B, SEL_HSCIF1_1),
|
||||
PINMUX_IPSR_MSEL(IP9_3_2, VI0_DATA1_VI0_B1, SEL_VI0_0),
|
||||
PINMUX_IPSR_MSEL(IP9_3_2, HCTS1_B, SEL_HSCIF1_1),
|
||||
PINMUX_IPSR_DATA(IP9_3_2, MT1_PWM),
|
||||
PINMUX_IPSR_DATA(IP9_4, VI0_DATA2_VI0_B2),
|
||||
PINMUX_IPSR_DATA(IP9_4, MMC1_D0),
|
||||
@ -1216,12 +1216,12 @@ static const u16 pinmux_data[] = {
|
||||
PINMUX_IPSR_DATA(IP9_11_10, MMC1_D5),
|
||||
PINMUX_IPSR_DATA(IP9_11_10, ARM_TRACEDATA_1),
|
||||
PINMUX_IPSR_DATA(IP9_13_12, VI0_G0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP9_13_12, SSI_SCK78_C, SEL_SSI7_2),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP9_13_12, IRQ0, SEL_INT0_0),
|
||||
PINMUX_IPSR_MSEL(IP9_13_12, SSI_SCK78_C, SEL_SSI7_2),
|
||||
PINMUX_IPSR_MSEL(IP9_13_12, IRQ0, SEL_INT0_0),
|
||||
PINMUX_IPSR_DATA(IP9_13_12, ARM_TRACEDATA_2),
|
||||
PINMUX_IPSR_DATA(IP9_15_14, VI0_G1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP9_15_14, SSI_WS78_C, SEL_SSI7_2),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP9_15_14, IRQ1, SEL_INT1_0),
|
||||
PINMUX_IPSR_MSEL(IP9_15_14, SSI_WS78_C, SEL_SSI7_2),
|
||||
PINMUX_IPSR_MSEL(IP9_15_14, IRQ1, SEL_INT1_0),
|
||||
PINMUX_IPSR_DATA(IP9_15_14, ARM_TRACEDATA_3),
|
||||
PINMUX_IPSR_DATA(IP9_18_16, VI0_G2),
|
||||
PINMUX_IPSR_DATA(IP9_18_16, ETH_TXD1),
|
||||
@ -1235,29 +1235,29 @@ static const u16 pinmux_data[] = {
|
||||
PINMUX_IPSR_DATA(IP9_21_19, TS_SDAT0),
|
||||
PINMUX_IPSR_DATA(IP9_23_22, VI0_G4),
|
||||
PINMUX_IPSR_DATA(IP9_23_22, ETH_TX_EN),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SD2_DAT0_B, SEL_SD2_1),
|
||||
PINMUX_IPSR_MSEL(IP9_23_22, SD2_DAT0_B, SEL_SD2_1),
|
||||
PINMUX_IPSR_DATA(IP9_23_22, ARM_TRACEDATA_6),
|
||||
PINMUX_IPSR_DATA(IP9_25_24, VI0_G5),
|
||||
PINMUX_IPSR_DATA(IP9_25_24, ETH_RX_ER),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SD2_DAT1_B, SEL_SD2_1),
|
||||
PINMUX_IPSR_MSEL(IP9_25_24, SD2_DAT1_B, SEL_SD2_1),
|
||||
PINMUX_IPSR_DATA(IP9_25_24, ARM_TRACEDATA_7),
|
||||
PINMUX_IPSR_DATA(IP9_27_26, VI0_G6),
|
||||
PINMUX_IPSR_DATA(IP9_27_26, ETH_RXD0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SD2_DAT2_B, SEL_SD2_1),
|
||||
PINMUX_IPSR_MSEL(IP9_27_26, SD2_DAT2_B, SEL_SD2_1),
|
||||
PINMUX_IPSR_DATA(IP9_27_26, ARM_TRACEDATA_8),
|
||||
PINMUX_IPSR_DATA(IP9_29_28, VI0_G7),
|
||||
PINMUX_IPSR_DATA(IP9_29_28, ETH_RXD1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP9_29_28, SD2_DAT3_B, SEL_SD2_1),
|
||||
PINMUX_IPSR_MSEL(IP9_29_28, SD2_DAT3_B, SEL_SD2_1),
|
||||
PINMUX_IPSR_DATA(IP9_29_28, ARM_TRACEDATA_9),
|
||||
|
||||
PINMUX_IPSR_DATA(IP10_2_0, VI0_R0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SSI_SDATA7_C, SEL_SSI7_2),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SCK1_C, SEL_SCIF1_2),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_2_0, DREQ1_B, SEL_EXBUS1_0),
|
||||
PINMUX_IPSR_MSEL(IP10_2_0, SSI_SDATA7_C, SEL_SSI7_2),
|
||||
PINMUX_IPSR_MSEL(IP10_2_0, SCK1_C, SEL_SCIF1_2),
|
||||
PINMUX_IPSR_MSEL(IP10_2_0, DREQ1_B, SEL_EXBUS1_0),
|
||||
PINMUX_IPSR_DATA(IP10_2_0, ARM_TRACEDATA_10),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_2_0, DREQ0_C, SEL_EXBUS0_2),
|
||||
PINMUX_IPSR_MSEL(IP10_2_0, DREQ0_C, SEL_EXBUS0_2),
|
||||
PINMUX_IPSR_DATA(IP10_5_3, VI0_R1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SSI_SDATA8_C, SEL_SSI8_2),
|
||||
PINMUX_IPSR_MSEL(IP10_5_3, SSI_SDATA8_C, SEL_SSI8_2),
|
||||
PINMUX_IPSR_DATA(IP10_5_3, DACK1_B),
|
||||
PINMUX_IPSR_DATA(IP10_5_3, ARM_TRACEDATA_11),
|
||||
PINMUX_IPSR_DATA(IP10_5_3, DACK0_C),
|
||||
@ -1265,74 +1265,74 @@ static const u16 pinmux_data[] = {
|
||||
PINMUX_IPSR_DATA(IP10_8_6, VI0_R2),
|
||||
PINMUX_IPSR_DATA(IP10_8_6, ETH_LINK),
|
||||
PINMUX_IPSR_DATA(IP10_8_6, SD2_CLK_B),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_8_6, IRQ2, SEL_INT2_0),
|
||||
PINMUX_IPSR_MSEL(IP10_8_6, IRQ2, SEL_INT2_0),
|
||||
PINMUX_IPSR_DATA(IP10_8_6, ARM_TRACEDATA_12),
|
||||
PINMUX_IPSR_DATA(IP10_11_9, VI0_R3),
|
||||
PINMUX_IPSR_DATA(IP10_11_9, ETH_MAGIC),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SD2_CMD_B, SEL_SD2_1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_11_9, IRQ3, SEL_INT3_0),
|
||||
PINMUX_IPSR_MSEL(IP10_11_9, SD2_CMD_B, SEL_SD2_1),
|
||||
PINMUX_IPSR_MSEL(IP10_11_9, IRQ3, SEL_INT3_0),
|
||||
PINMUX_IPSR_DATA(IP10_11_9, ARM_TRACEDATA_13),
|
||||
PINMUX_IPSR_DATA(IP10_14_12, VI0_R4),
|
||||
PINMUX_IPSR_DATA(IP10_14_12, ETH_REFCLK),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SD2_CD_B, SEL_SD2_1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_14_12, HSPI_CLK1_B, SEL_HSPI1_1),
|
||||
PINMUX_IPSR_MSEL(IP10_14_12, SD2_CD_B, SEL_SD2_1),
|
||||
PINMUX_IPSR_MSEL(IP10_14_12, HSPI_CLK1_B, SEL_HSPI1_1),
|
||||
PINMUX_IPSR_DATA(IP10_14_12, ARM_TRACEDATA_14),
|
||||
PINMUX_IPSR_DATA(IP10_14_12, MT1_CLK),
|
||||
PINMUX_IPSR_DATA(IP10_14_12, TS_SCK0),
|
||||
PINMUX_IPSR_DATA(IP10_17_15, VI0_R5),
|
||||
PINMUX_IPSR_DATA(IP10_17_15, ETH_TXD0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_17_15, SD2_WP_B, SEL_SD2_1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_17_15, HSPI_CS1_B, SEL_HSPI1_1),
|
||||
PINMUX_IPSR_MSEL(IP10_17_15, SD2_WP_B, SEL_SD2_1),
|
||||
PINMUX_IPSR_MSEL(IP10_17_15, HSPI_CS1_B, SEL_HSPI1_1),
|
||||
PINMUX_IPSR_DATA(IP10_17_15, ARM_TRACEDATA_15),
|
||||
PINMUX_IPSR_DATA(IP10_17_15, MT1_D),
|
||||
PINMUX_IPSR_DATA(IP10_17_15, TS_SDEN0),
|
||||
PINMUX_IPSR_DATA(IP10_20_18, VI0_R6),
|
||||
PINMUX_IPSR_DATA(IP10_20_18, ETH_MDC),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_20_18, DREQ2_C, SEL_EXBUS2_2),
|
||||
PINMUX_IPSR_MSEL(IP10_20_18, DREQ2_C, SEL_EXBUS2_2),
|
||||
PINMUX_IPSR_DATA(IP10_20_18, HSPI_TX1_B),
|
||||
PINMUX_IPSR_DATA(IP10_20_18, TRACECLK),
|
||||
PINMUX_IPSR_DATA(IP10_20_18, MT1_BEN),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_20_18, PWMFSW0_D, SEL_PWMFSW_3),
|
||||
PINMUX_IPSR_MSEL(IP10_20_18, PWMFSW0_D, SEL_PWMFSW_3),
|
||||
PINMUX_IPSR_DATA(IP10_23_21, VI0_R7),
|
||||
PINMUX_IPSR_DATA(IP10_23_21, ETH_MDIO),
|
||||
PINMUX_IPSR_DATA(IP10_23_21, DACK2_C),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_23_21, HSPI_RX1_B, SEL_HSPI1_1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_23_21, SCIF_CLK_D, SEL_SCIF_3),
|
||||
PINMUX_IPSR_MSEL(IP10_23_21, HSPI_RX1_B, SEL_HSPI1_1),
|
||||
PINMUX_IPSR_MSEL(IP10_23_21, SCIF_CLK_D, SEL_SCIF_3),
|
||||
PINMUX_IPSR_DATA(IP10_23_21, TRACECTL),
|
||||
PINMUX_IPSR_DATA(IP10_23_21, MT1_PEN),
|
||||
PINMUX_IPSR_DATA(IP10_25_24, VI1_CLK),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_25_24, SIM_D, SEL_SIM_0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_25_24, SDA3, SEL_I2C3_0),
|
||||
PINMUX_IPSR_MSEL(IP10_25_24, SIM_D, SEL_SIM_0),
|
||||
PINMUX_IPSR_MSEL(IP10_25_24, SDA3, SEL_I2C3_0),
|
||||
PINMUX_IPSR_DATA(IP10_28_26, VI1_HSYNC),
|
||||
PINMUX_IPSR_DATA(IP10_28_26, VI3_CLK),
|
||||
PINMUX_IPSR_DATA(IP10_28_26, SSI_SCK4),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_28_26, GPS_SIGN_C, SEL_GPS_2),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_28_26, PWMFSW0_E, SEL_PWMFSW_4),
|
||||
PINMUX_IPSR_MSEL(IP10_28_26, GPS_SIGN_C, SEL_GPS_2),
|
||||
PINMUX_IPSR_MSEL(IP10_28_26, PWMFSW0_E, SEL_PWMFSW_4),
|
||||
PINMUX_IPSR_DATA(IP10_31_29, VI1_VSYNC),
|
||||
PINMUX_IPSR_DATA(IP10_31_29, AUDIO_CLKOUT_C),
|
||||
PINMUX_IPSR_DATA(IP10_31_29, SSI_WS4),
|
||||
PINMUX_IPSR_DATA(IP10_31_29, SIM_CLK),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_31_29, GPS_MAG_C, SEL_GPS_2),
|
||||
PINMUX_IPSR_MSEL(IP10_31_29, GPS_MAG_C, SEL_GPS_2),
|
||||
PINMUX_IPSR_DATA(IP10_31_29, SPV_TRST),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP10_31_29, SCL3, SEL_I2C3_0),
|
||||
PINMUX_IPSR_MSEL(IP10_31_29, SCL3, SEL_I2C3_0),
|
||||
|
||||
PINMUX_IPSR_DATA(IP11_2_0, VI1_DATA0_VI1_B0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SD2_DAT0, SEL_SD2_0),
|
||||
PINMUX_IPSR_MSEL(IP11_2_0, SD2_DAT0, SEL_SD2_0),
|
||||
PINMUX_IPSR_DATA(IP11_2_0, SIM_RST),
|
||||
PINMUX_IPSR_DATA(IP11_2_0, SPV_TCK),
|
||||
PINMUX_IPSR_DATA(IP11_2_0, ADICLK_B),
|
||||
PINMUX_IPSR_DATA(IP11_5_3, VI1_DATA1_VI1_B1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SD2_DAT1, SEL_SD2_0),
|
||||
PINMUX_IPSR_MSEL(IP11_5_3, SD2_DAT1, SEL_SD2_0),
|
||||
PINMUX_IPSR_DATA(IP11_5_3, MT0_CLK),
|
||||
PINMUX_IPSR_DATA(IP11_5_3, SPV_TMS),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP11_5_3, ADICS_B_SAMP_B, SEL_ADI_1),
|
||||
PINMUX_IPSR_MSEL(IP11_5_3, ADICS_B_SAMP_B, SEL_ADI_1),
|
||||
PINMUX_IPSR_DATA(IP11_8_6, VI1_DATA2_VI1_B2),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SD2_DAT2, SEL_SD2_0),
|
||||
PINMUX_IPSR_MSEL(IP11_8_6, SD2_DAT2, SEL_SD2_0),
|
||||
PINMUX_IPSR_DATA(IP11_8_6, MT0_D),
|
||||
PINMUX_IPSR_DATA(IP11_8_6, SPVTDI),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP11_8_6, ADIDATA_B, SEL_ADI_1),
|
||||
PINMUX_IPSR_MSEL(IP11_8_6, ADIDATA_B, SEL_ADI_1),
|
||||
PINMUX_IPSR_DATA(IP11_11_9, VI1_DATA3_VI1_B3),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP11_11_9, SD2_DAT3, SEL_SD2_0),
|
||||
PINMUX_IPSR_MSEL(IP11_11_9, SD2_DAT3, SEL_SD2_0),
|
||||
PINMUX_IPSR_DATA(IP11_11_9, MT0_BEN),
|
||||
PINMUX_IPSR_DATA(IP11_11_9, SPV_TDO),
|
||||
PINMUX_IPSR_DATA(IP11_11_9, ADICHS0_B),
|
||||
@ -1340,74 +1340,74 @@ static const u16 pinmux_data[] = {
|
||||
PINMUX_IPSR_DATA(IP11_14_12, SD2_CLK),
|
||||
PINMUX_IPSR_DATA(IP11_14_12, MT0_PEN),
|
||||
PINMUX_IPSR_DATA(IP11_14_12, SPA_TRST),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP11_14_12, HSPI_CLK1_D, SEL_HSPI1_3),
|
||||
PINMUX_IPSR_MSEL(IP11_14_12, HSPI_CLK1_D, SEL_HSPI1_3),
|
||||
PINMUX_IPSR_DATA(IP11_14_12, ADICHS1_B),
|
||||
PINMUX_IPSR_DATA(IP11_17_15, VI1_DATA5_VI1_B5),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP11_17_15, SD2_CMD, SEL_SD2_0),
|
||||
PINMUX_IPSR_MSEL(IP11_17_15, SD2_CMD, SEL_SD2_0),
|
||||
PINMUX_IPSR_DATA(IP11_17_15, MT0_SYNC),
|
||||
PINMUX_IPSR_DATA(IP11_17_15, SPA_TCK),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP11_17_15, HSPI_CS1_D, SEL_HSPI1_3),
|
||||
PINMUX_IPSR_MSEL(IP11_17_15, HSPI_CS1_D, SEL_HSPI1_3),
|
||||
PINMUX_IPSR_DATA(IP11_17_15, ADICHS2_B),
|
||||
PINMUX_IPSR_DATA(IP11_20_18, VI1_DATA6_VI1_B6),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SD2_CD, SEL_SD2_0),
|
||||
PINMUX_IPSR_MSEL(IP11_20_18, SD2_CD, SEL_SD2_0),
|
||||
PINMUX_IPSR_DATA(IP11_20_18, MT0_VCXO),
|
||||
PINMUX_IPSR_DATA(IP11_20_18, SPA_TMS),
|
||||
PINMUX_IPSR_DATA(IP11_20_18, HSPI_TX1_D),
|
||||
PINMUX_IPSR_DATA(IP11_23_21, VI1_DATA7_VI1_B7),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP11_23_21, SD2_WP, SEL_SD2_0),
|
||||
PINMUX_IPSR_MSEL(IP11_23_21, SD2_WP, SEL_SD2_0),
|
||||
PINMUX_IPSR_DATA(IP11_23_21, MT0_PWM),
|
||||
PINMUX_IPSR_DATA(IP11_23_21, SPA_TDI),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP11_23_21, HSPI_RX1_D, SEL_HSPI1_3),
|
||||
PINMUX_IPSR_MSEL(IP11_23_21, HSPI_RX1_D, SEL_HSPI1_3),
|
||||
PINMUX_IPSR_DATA(IP11_26_24, VI1_G0),
|
||||
PINMUX_IPSR_DATA(IP11_26_24, VI3_DATA0),
|
||||
PINMUX_IPSR_DATA(IP11_26_24, TS_SCK1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP11_26_24, DREQ2_B, SEL_EXBUS2_1),
|
||||
PINMUX_IPSR_MSEL(IP11_26_24, DREQ2_B, SEL_EXBUS2_1),
|
||||
PINMUX_IPSR_DATA(IP11_26_24, TX2),
|
||||
PINMUX_IPSR_DATA(IP11_26_24, SPA_TDO),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP11_26_24, HCTS0_B, SEL_HSCIF0_1),
|
||||
PINMUX_IPSR_MSEL(IP11_26_24, HCTS0_B, SEL_HSCIF0_1),
|
||||
PINMUX_IPSR_DATA(IP11_29_27, VI1_G1),
|
||||
PINMUX_IPSR_DATA(IP11_29_27, VI3_DATA1),
|
||||
PINMUX_IPSR_DATA(IP11_29_27, SSI_SCK1),
|
||||
PINMUX_IPSR_DATA(IP11_29_27, TS_SDEN1),
|
||||
PINMUX_IPSR_DATA(IP11_29_27, DACK2_B),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP11_29_27, RX2, SEL_SCIF2_0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP11_29_27, HRTS0_B, SEL_HSCIF0_1),
|
||||
PINMUX_IPSR_MSEL(IP11_29_27, RX2, SEL_SCIF2_0),
|
||||
PINMUX_IPSR_MSEL(IP11_29_27, HRTS0_B, SEL_HSCIF0_1),
|
||||
|
||||
PINMUX_IPSR_DATA(IP12_2_0, VI1_G2),
|
||||
PINMUX_IPSR_DATA(IP12_2_0, VI3_DATA2),
|
||||
PINMUX_IPSR_DATA(IP12_2_0, SSI_WS1),
|
||||
PINMUX_IPSR_DATA(IP12_2_0, TS_SPSYNC1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP12_2_0, SCK2, SEL_SCIF2_0),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP12_2_0, HSCK0_B, SEL_HSCIF0_1),
|
||||
PINMUX_IPSR_MSEL(IP12_2_0, SCK2, SEL_SCIF2_0),
|
||||
PINMUX_IPSR_MSEL(IP12_2_0, HSCK0_B, SEL_HSCIF0_1),
|
||||
PINMUX_IPSR_DATA(IP12_5_3, VI1_G3),
|
||||
PINMUX_IPSR_DATA(IP12_5_3, VI3_DATA3),
|
||||
PINMUX_IPSR_DATA(IP12_5_3, SSI_SCK2),
|
||||
PINMUX_IPSR_DATA(IP12_5_3, TS_SDAT1),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP12_5_3, SCL1_C, SEL_I2C1_2),
|
||||
PINMUX_IPSR_MSEL(IP12_5_3, SCL1_C, SEL_I2C1_2),
|
||||
PINMUX_IPSR_DATA(IP12_5_3, HTX0_B),
|
||||
PINMUX_IPSR_DATA(IP12_8_6, VI1_G4),
|
||||
PINMUX_IPSR_DATA(IP12_8_6, VI3_DATA4),
|
||||
PINMUX_IPSR_DATA(IP12_8_6, SSI_WS2),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP12_8_6, SDA1_C, SEL_I2C1_2),
|
||||
PINMUX_IPSR_MSEL(IP12_8_6, SDA1_C, SEL_I2C1_2),
|
||||
PINMUX_IPSR_DATA(IP12_8_6, SIM_RST_B),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP12_8_6, HRX0_B, SEL_HSCIF0_1),
|
||||
PINMUX_IPSR_MSEL(IP12_8_6, HRX0_B, SEL_HSCIF0_1),
|
||||
PINMUX_IPSR_DATA(IP12_11_9, VI1_G5),
|
||||
PINMUX_IPSR_DATA(IP12_11_9, VI3_DATA5),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP12_11_9, GPS_CLK, SEL_GPS_0),
|
||||
PINMUX_IPSR_MSEL(IP12_11_9, GPS_CLK, SEL_GPS_0),
|
||||
PINMUX_IPSR_DATA(IP12_11_9, FSE),
|
||||
PINMUX_IPSR_DATA(IP12_11_9, TX4_B),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP12_11_9, SIM_D_B, SEL_SIM_1),
|
||||
PINMUX_IPSR_MSEL(IP12_11_9, SIM_D_B, SEL_SIM_1),
|
||||
PINMUX_IPSR_DATA(IP12_14_12, VI1_G6),
|
||||
PINMUX_IPSR_DATA(IP12_14_12, VI3_DATA6),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP12_14_12, GPS_SIGN, SEL_GPS_0),
|
||||
PINMUX_IPSR_MSEL(IP12_14_12, GPS_SIGN, SEL_GPS_0),
|
||||
PINMUX_IPSR_DATA(IP12_14_12, FRB),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP12_14_12, RX4_B, SEL_SCIF4_1),
|
||||
PINMUX_IPSR_MSEL(IP12_14_12, RX4_B, SEL_SCIF4_1),
|
||||
PINMUX_IPSR_DATA(IP12_14_12, SIM_CLK_B),
|
||||
PINMUX_IPSR_DATA(IP12_17_15, VI1_G7),
|
||||
PINMUX_IPSR_DATA(IP12_17_15, VI3_DATA7),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP12_17_15, GPS_MAG, SEL_GPS_0),
|
||||
PINMUX_IPSR_MSEL(IP12_17_15, GPS_MAG, SEL_GPS_0),
|
||||
PINMUX_IPSR_DATA(IP12_17_15, FCE),
|
||||
PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SCK4_B, SEL_SCIF4_1),
|
||||
PINMUX_IPSR_MSEL(IP12_17_15, SCK4_B, SEL_SCIF4_1),
|
||||
};
|
||||
|
||||
static const struct sh_pfc_pin pinmux_pins[] = {
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
2817
drivers/pinctrl/sh-pfc/pfc-r8a7795.c
Normal file
2817
drivers/pinctrl/sh-pfc/pfc-r8a7795.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -3649,38 +3649,38 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
|
||||
};
|
||||
|
||||
static const struct pinmux_irq pinmux_irqs[] = {
|
||||
PINMUX_IRQ(irq_pin(0), 11),
|
||||
PINMUX_IRQ(irq_pin(1), 10),
|
||||
PINMUX_IRQ(irq_pin(2), 149),
|
||||
PINMUX_IRQ(irq_pin(3), 224),
|
||||
PINMUX_IRQ(irq_pin(4), 159),
|
||||
PINMUX_IRQ(irq_pin(5), 227),
|
||||
PINMUX_IRQ(irq_pin(6), 147),
|
||||
PINMUX_IRQ(irq_pin(7), 150),
|
||||
PINMUX_IRQ(irq_pin(8), 223),
|
||||
PINMUX_IRQ(irq_pin(9), 56, 308),
|
||||
PINMUX_IRQ(irq_pin(10), 54),
|
||||
PINMUX_IRQ(irq_pin(11), 238),
|
||||
PINMUX_IRQ(irq_pin(12), 156),
|
||||
PINMUX_IRQ(irq_pin(13), 239),
|
||||
PINMUX_IRQ(irq_pin(14), 251),
|
||||
PINMUX_IRQ(irq_pin(15), 0),
|
||||
PINMUX_IRQ(irq_pin(16), 249),
|
||||
PINMUX_IRQ(irq_pin(17), 234),
|
||||
PINMUX_IRQ(irq_pin(18), 13),
|
||||
PINMUX_IRQ(irq_pin(19), 9),
|
||||
PINMUX_IRQ(irq_pin(20), 14),
|
||||
PINMUX_IRQ(irq_pin(21), 15),
|
||||
PINMUX_IRQ(irq_pin(22), 40),
|
||||
PINMUX_IRQ(irq_pin(23), 53),
|
||||
PINMUX_IRQ(irq_pin(24), 118),
|
||||
PINMUX_IRQ(irq_pin(25), 164),
|
||||
PINMUX_IRQ(irq_pin(26), 115),
|
||||
PINMUX_IRQ(irq_pin(27), 116),
|
||||
PINMUX_IRQ(irq_pin(28), 117),
|
||||
PINMUX_IRQ(irq_pin(29), 28),
|
||||
PINMUX_IRQ(irq_pin(30), 27),
|
||||
PINMUX_IRQ(irq_pin(31), 26),
|
||||
PINMUX_IRQ(11), /* IRQ0 */
|
||||
PINMUX_IRQ(10), /* IRQ1 */
|
||||
PINMUX_IRQ(149), /* IRQ2 */
|
||||
PINMUX_IRQ(224), /* IRQ3 */
|
||||
PINMUX_IRQ(159), /* IRQ4 */
|
||||
PINMUX_IRQ(227), /* IRQ5 */
|
||||
PINMUX_IRQ(147), /* IRQ6 */
|
||||
PINMUX_IRQ(150), /* IRQ7 */
|
||||
PINMUX_IRQ(223), /* IRQ8 */
|
||||
PINMUX_IRQ(56, 308), /* IRQ9 */
|
||||
PINMUX_IRQ(54), /* IRQ10 */
|
||||
PINMUX_IRQ(238), /* IRQ11 */
|
||||
PINMUX_IRQ(156), /* IRQ12 */
|
||||
PINMUX_IRQ(239), /* IRQ13 */
|
||||
PINMUX_IRQ(251), /* IRQ14 */
|
||||
PINMUX_IRQ(0), /* IRQ15 */
|
||||
PINMUX_IRQ(249), /* IRQ16 */
|
||||
PINMUX_IRQ(234), /* IRQ17 */
|
||||
PINMUX_IRQ(13), /* IRQ18 */
|
||||
PINMUX_IRQ(9), /* IRQ19 */
|
||||
PINMUX_IRQ(14), /* IRQ20 */
|
||||
PINMUX_IRQ(15), /* IRQ21 */
|
||||
PINMUX_IRQ(40), /* IRQ22 */
|
||||
PINMUX_IRQ(53), /* IRQ23 */
|
||||
PINMUX_IRQ(118), /* IRQ24 */
|
||||
PINMUX_IRQ(164), /* IRQ25 */
|
||||
PINMUX_IRQ(115), /* IRQ26 */
|
||||
PINMUX_IRQ(116), /* IRQ27 */
|
||||
PINMUX_IRQ(117), /* IRQ28 */
|
||||
PINMUX_IRQ(28), /* IRQ29 */
|
||||
PINMUX_IRQ(27), /* IRQ30 */
|
||||
PINMUX_IRQ(26), /* IRQ31 */
|
||||
};
|
||||
|
||||
/* -----------------------------------------------------------------------------
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -98,17 +98,11 @@ struct pinmux_data_reg {
|
||||
.enum_ids = (const u16 [r_width]) \
|
||||
|
||||
struct pinmux_irq {
|
||||
int irq;
|
||||
const short *gpios;
|
||||
};
|
||||
|
||||
#ifdef CONFIG_ARCH_MULTIPLATFORM
|
||||
#define PINMUX_IRQ(irq_nr, ids...) \
|
||||
#define PINMUX_IRQ(ids...) \
|
||||
{ .gpios = (const short []) { ids, -1 } }
|
||||
#else
|
||||
#define PINMUX_IRQ(irq_nr, ids...) \
|
||||
{ .irq = irq_nr, .gpios = (const short []) { ids, -1 } }
|
||||
#endif
|
||||
|
||||
struct pinmux_range {
|
||||
u16 begin;
|
||||
@ -143,8 +137,10 @@ struct sh_pfc_soc_info {
|
||||
const struct sh_pfc_function *functions;
|
||||
unsigned int nr_functions;
|
||||
|
||||
#ifdef CONFIG_SUPERH
|
||||
const struct pinmux_func *func_gpios;
|
||||
unsigned int nr_func_gpios;
|
||||
#endif
|
||||
|
||||
const struct pinmux_cfg_reg *cfg_regs;
|
||||
const struct pinmux_data_reg *data_regs;
|
||||
@ -177,8 +173,6 @@ struct sh_pfc_soc_info {
|
||||
#define PINMUX_IPSR_NOFN(ipsr, fn, ms) \
|
||||
PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##ms)
|
||||
#define PINMUX_IPSR_MSEL(ipsr, fn, ms) \
|
||||
PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr, FN_##ms)
|
||||
#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) \
|
||||
PINMUX_DATA(fn##_MARK, FN_##ms, FN_##ipsr, FN_##fn)
|
||||
|
||||
/*
|
||||
|
||||
Loading…
Reference in New Issue
Block a user