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spi: s3c64xx: Fix large transfers with DMA
The COUNT_VALUE in the PACKET_CNT register is 16-bit so the maximum
value is 65535. Asking the driver to transfer a larger size currently
leads to the DMA transfer timing out. Implement ->max_transfer_size()
and have the core split the transfer as needed.
Fixes: 230d42d422
("spi: Add s3c64xx SPI Controller driver")
Signed-off-by: Vincent Whitchurch <vincent.whitchurch@axis.com>
Link: https://lore.kernel.org/r/20220927112117.77599-5-vincent.whitchurch@axis.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
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@ -84,6 +84,7 @@
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#define S3C64XX_SPI_ST_TX_FIFORDY (1<<0)
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#define S3C64XX_SPI_ST_TX_FIFORDY (1<<0)
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#define S3C64XX_SPI_PACKET_CNT_EN (1<<16)
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#define S3C64XX_SPI_PACKET_CNT_EN (1<<16)
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#define S3C64XX_SPI_PACKET_CNT_MASK GENMASK(15, 0)
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#define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4)
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#define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4)
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#define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3)
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#define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3)
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@ -711,6 +712,13 @@ static int s3c64xx_spi_prepare_message(struct spi_master *master,
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return 0;
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return 0;
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}
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}
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static size_t s3c64xx_spi_max_transfer_size(struct spi_device *spi)
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{
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struct spi_controller *ctlr = spi->controller;
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return ctlr->can_dma ? S3C64XX_SPI_PACKET_CNT_MASK : SIZE_MAX;
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}
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static int s3c64xx_spi_transfer_one(struct spi_master *master,
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static int s3c64xx_spi_transfer_one(struct spi_master *master,
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struct spi_device *spi,
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struct spi_device *spi,
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struct spi_transfer *xfer)
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struct spi_transfer *xfer)
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@ -1152,6 +1160,7 @@ static int s3c64xx_spi_probe(struct platform_device *pdev)
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master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
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master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
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master->prepare_message = s3c64xx_spi_prepare_message;
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master->prepare_message = s3c64xx_spi_prepare_message;
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master->transfer_one = s3c64xx_spi_transfer_one;
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master->transfer_one = s3c64xx_spi_transfer_one;
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master->max_transfer_size = s3c64xx_spi_max_transfer_size;
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master->num_chipselect = sci->num_cs;
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master->num_chipselect = sci->num_cs;
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master->use_gpio_descriptors = true;
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master->use_gpio_descriptors = true;
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master->dma_alignment = 8;
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master->dma_alignment = 8;
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