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drm/radeon: implement UVD hw workarounds for R6xx v3

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Only the essentials, cause this hw generation is really buggy.

v2: start supporting RV670,RV620 and RV635 as well
v3: activate more workarounds

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Christian König 2013-04-25 09:02:14 +02:00 committed by Alex Deucher
parent 856754c3a2
commit 115365e8a3
2 changed files with 28 additions and 1 deletions
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3
drivers/gpu/drm/radeon/r600d.h
View File

@ -330,6 +330,7 @@
#define HDP_TILING_CONFIG 0x2F3C
#define HDP_DEBUG1 0x2F34
#define MC_CONFIG 0x2000
#define MC_VM_AGP_TOP 0x2184
#define MC_VM_AGP_BOT 0x2188
#define MC_VM_AGP_BASE 0x218C
@ -375,6 +376,8 @@
#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194
#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198
#define RS_DQ_RD_RET_CONF 0x2348
#define PA_CL_ENHANCE 0x8A14
#define CLIP_VTX_REORDER_ENA (1 << 0)
#define NUM_CLIP_SEQ(x) ((x) << 1)

26
drivers/gpu/drm/radeon/uvd_v1_0.c
View File

@ -207,8 +207,32 @@ done:
/* lower clocks again */
radeon_set_uvd_clocks(rdev, 0, 0);
if (!r)
if (!r) {
switch (rdev->family) {
case CHIP_RV610:
case CHIP_RV630:
case CHIP_RV620:
/* 64byte granularity workaround */
WREG32(MC_CONFIG, 0);
WREG32(MC_CONFIG, 1 << 4);
WREG32(RS_DQ_RD_RET_CONF, 0x3f);
WREG32(MC_CONFIG, 0x1f);
/* fall through */
case CHIP_RV670:
case CHIP_RV635:
/* write clean workaround */
WREG32_P(UVD_VCPU_CNTL, 0x10, ~0x10);
break;
default:
/* TODO: Do we need more? */
break;
}
DRM_INFO("UVD initialized successfully.\n");
}
return r;
}