mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-27 14:43:58 +08:00
rtc: remove bfin driver
The blackfin architecture is getting removed, so this one is now obsolete. Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-by: Aaron Wu <aaron.wu@analog.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
parent
fca94ec613
commit
111f750389
@ -1434,16 +1434,6 @@ config RTC_DRV_AU1XXX
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This driver can also be built as a module. If so, the module
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will be called rtc-au1xxx.
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config RTC_DRV_BFIN
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tristate "Blackfin On-Chip RTC"
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depends on BLACKFIN && !BF561
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help
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If you say yes here you will get support for the
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Blackfin On-Chip Real Time Clock.
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This driver can also be built as a module. If so, the module
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will be called rtc-bfin.
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config RTC_DRV_RS5C313
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tristate "Ricoh RS5C313"
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depends on SH_LANDISK
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@ -36,7 +36,6 @@ obj-$(CONFIG_RTC_DRV_ASM9260) += rtc-asm9260.o
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obj-$(CONFIG_RTC_DRV_AT91RM9200)+= rtc-at91rm9200.o
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obj-$(CONFIG_RTC_DRV_AT91SAM9) += rtc-at91sam9.o
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obj-$(CONFIG_RTC_DRV_AU1XXX) += rtc-au1xxx.o
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obj-$(CONFIG_RTC_DRV_BFIN) += rtc-bfin.o
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obj-$(CONFIG_RTC_DRV_BRCMSTB) += rtc-brcmstb-waketimer.o
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obj-$(CONFIG_RTC_DRV_BQ32K) += rtc-bq32k.o
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obj-$(CONFIG_RTC_DRV_BQ4802) += rtc-bq4802.o
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@ -1,448 +0,0 @@
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/*
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* Blackfin On-Chip Real Time Clock Driver
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* Supports BF51x/BF52x/BF53[123]/BF53[467]/BF54x
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*
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* Copyright 2004-2010 Analog Devices Inc.
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*
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* Enter bugs at http://blackfin.uclinux.org/
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*
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* Licensed under the GPL-2 or later.
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*/
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/* The biggest issue we deal with in this driver is that register writes are
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* synced to the RTC frequency of 1Hz. So if you write to a register and
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* attempt to write again before the first write has completed, the new write
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* is simply discarded. This can easily be troublesome if userspace disables
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* one event (say periodic) and then right after enables an event (say alarm).
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* Since all events are maintained in the same interrupt mask register, if
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* we wrote to it to disable the first event and then wrote to it again to
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* enable the second event, that second event would not be enabled as the
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* write would be discarded and things quickly fall apart.
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*
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* To keep this delay from significantly degrading performance (we, in theory,
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* would have to sleep for up to 1 second every time we wanted to write a
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* register), we only check the write pending status before we start to issue
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* a new write. We bank on the idea that it doesn't matter when the sync
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* happens so long as we don't attempt another write before it does. The only
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* time userspace would take this penalty is when they try and do multiple
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* operations right after another ... but in this case, they need to take the
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* sync penalty, so we should be OK.
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*
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* Also note that the RTC_ISTAT register does not suffer this penalty; its
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* writes to clear status registers complete immediately.
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*/
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/* It may seem odd that there is no SWCNT code in here (which would be exposed
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* via the periodic interrupt event, or PIE). Since the Blackfin RTC peripheral
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* runs in units of seconds (N/HZ) but the Linux framework runs in units of HZ
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* (2^N HZ), there is no point in keeping code that only provides 1 HZ PIEs.
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* The same exact behavior can be accomplished by using the update interrupt
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* event (UIE). Maybe down the line the RTC peripheral will suck less in which
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* case we can re-introduce PIE support.
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*/
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#include <linux/bcd.h>
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#include <linux/completion.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/rtc.h>
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#include <linux/seq_file.h>
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#include <linux/slab.h>
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#include <asm/blackfin.h>
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#define dev_dbg_stamp(dev) dev_dbg(dev, "%s:%i: here i am\n", __func__, __LINE__)
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struct bfin_rtc {
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struct rtc_device *rtc_dev;
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struct rtc_time rtc_alarm;
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u16 rtc_wrote_regs;
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};
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/* Bit values for the ISTAT / ICTL registers */
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#define RTC_ISTAT_WRITE_COMPLETE 0x8000
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#define RTC_ISTAT_WRITE_PENDING 0x4000
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#define RTC_ISTAT_ALARM_DAY 0x0040
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#define RTC_ISTAT_24HR 0x0020
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#define RTC_ISTAT_HOUR 0x0010
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#define RTC_ISTAT_MIN 0x0008
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#define RTC_ISTAT_SEC 0x0004
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#define RTC_ISTAT_ALARM 0x0002
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#define RTC_ISTAT_STOPWATCH 0x0001
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/* Shift values for RTC_STAT register */
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#define DAY_BITS_OFF 17
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#define HOUR_BITS_OFF 12
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#define MIN_BITS_OFF 6
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#define SEC_BITS_OFF 0
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/* Some helper functions to convert between the common RTC notion of time
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* and the internal Blackfin notion that is encoded in 32bits.
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*/
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static inline u32 rtc_time_to_bfin(unsigned long now)
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{
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u32 sec = (now % 60);
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u32 min = (now % (60 * 60)) / 60;
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u32 hour = (now % (60 * 60 * 24)) / (60 * 60);
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u32 days = (now / (60 * 60 * 24));
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return (sec << SEC_BITS_OFF) +
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(min << MIN_BITS_OFF) +
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(hour << HOUR_BITS_OFF) +
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(days << DAY_BITS_OFF);
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}
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static inline unsigned long rtc_bfin_to_time(u32 rtc_bfin)
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{
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return (((rtc_bfin >> SEC_BITS_OFF) & 0x003F)) +
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(((rtc_bfin >> MIN_BITS_OFF) & 0x003F) * 60) +
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(((rtc_bfin >> HOUR_BITS_OFF) & 0x001F) * 60 * 60) +
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(((rtc_bfin >> DAY_BITS_OFF) & 0x7FFF) * 60 * 60 * 24);
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}
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static inline void rtc_bfin_to_tm(u32 rtc_bfin, struct rtc_time *tm)
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{
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rtc_time_to_tm(rtc_bfin_to_time(rtc_bfin), tm);
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}
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/**
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* bfin_rtc_sync_pending - make sure pending writes have complete
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*
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* Wait for the previous write to a RTC register to complete.
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* Unfortunately, we can't sleep here as that introduces a race condition when
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* turning on interrupt events. Consider this:
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* - process sets alarm
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* - process enables alarm
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* - process sleeps while waiting for rtc write to sync
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* - interrupt fires while process is sleeping
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* - interrupt acks the event by writing to ISTAT
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* - interrupt sets the WRITE PENDING bit
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* - interrupt handler finishes
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* - process wakes up, sees WRITE PENDING bit set, goes to sleep
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* - interrupt fires while process is sleeping
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* If anyone can point out the obvious solution here, i'm listening :). This
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* shouldn't be an issue on an SMP or preempt system as this function should
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* only be called with the rtc lock held.
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*
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* Other options:
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* - disable PREN so the sync happens at 32.768kHZ ... but this changes the
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* inc rate for all RTC registers from 1HZ to 32.768kHZ ...
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* - use the write complete IRQ
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*/
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/*
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static void bfin_rtc_sync_pending_polled(void)
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{
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while (!(bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_COMPLETE))
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if (!(bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_PENDING))
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break;
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bfin_write_RTC_ISTAT(RTC_ISTAT_WRITE_COMPLETE);
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}
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*/
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static DECLARE_COMPLETION(bfin_write_complete);
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static void bfin_rtc_sync_pending(struct device *dev)
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{
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dev_dbg_stamp(dev);
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while (bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_PENDING)
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wait_for_completion_timeout(&bfin_write_complete, HZ * 5);
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dev_dbg_stamp(dev);
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}
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/**
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* bfin_rtc_reset - set RTC to sane/known state
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*
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* Initialize the RTC. Enable pre-scaler to scale RTC clock
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* to 1Hz and clear interrupt/status registers.
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*/
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static void bfin_rtc_reset(struct device *dev, u16 rtc_ictl)
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{
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struct bfin_rtc *rtc = dev_get_drvdata(dev);
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dev_dbg_stamp(dev);
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bfin_rtc_sync_pending(dev);
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bfin_write_RTC_PREN(0x1);
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bfin_write_RTC_ICTL(rtc_ictl);
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bfin_write_RTC_ALARM(0);
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bfin_write_RTC_ISTAT(0xFFFF);
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rtc->rtc_wrote_regs = 0;
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}
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/**
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* bfin_rtc_interrupt - handle interrupt from RTC
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*
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* Since we handle all RTC events here, we have to make sure the requested
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* interrupt is enabled (in RTC_ICTL) as the event status register (RTC_ISTAT)
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* always gets updated regardless of the interrupt being enabled. So when one
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* even we care about (e.g. stopwatch) goes off, we don't want to turn around
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* and say that other events have happened as well (e.g. second). We do not
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* have to worry about pending writes to the RTC_ICTL register as interrupts
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* only fire if they are enabled in the RTC_ICTL register.
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*/
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static irqreturn_t bfin_rtc_interrupt(int irq, void *dev_id)
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{
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struct device *dev = dev_id;
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struct bfin_rtc *rtc = dev_get_drvdata(dev);
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unsigned long events = 0;
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bool write_complete = false;
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u16 rtc_istat, rtc_istat_clear, rtc_ictl, bits;
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dev_dbg_stamp(dev);
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rtc_istat = bfin_read_RTC_ISTAT();
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rtc_ictl = bfin_read_RTC_ICTL();
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rtc_istat_clear = 0;
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bits = RTC_ISTAT_WRITE_COMPLETE;
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if (rtc_istat & bits) {
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rtc_istat_clear |= bits;
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write_complete = true;
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complete(&bfin_write_complete);
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}
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bits = (RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY);
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if (rtc_ictl & bits) {
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if (rtc_istat & bits) {
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rtc_istat_clear |= bits;
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events |= RTC_AF | RTC_IRQF;
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}
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}
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bits = RTC_ISTAT_SEC;
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if (rtc_ictl & bits) {
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if (rtc_istat & bits) {
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rtc_istat_clear |= bits;
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events |= RTC_UF | RTC_IRQF;
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}
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}
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if (events)
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rtc_update_irq(rtc->rtc_dev, 1, events);
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if (write_complete || events) {
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bfin_write_RTC_ISTAT(rtc_istat_clear);
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return IRQ_HANDLED;
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} else
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return IRQ_NONE;
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}
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static void bfin_rtc_int_set(u16 rtc_int)
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{
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bfin_write_RTC_ISTAT(rtc_int);
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bfin_write_RTC_ICTL(bfin_read_RTC_ICTL() | rtc_int);
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}
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static void bfin_rtc_int_clear(u16 rtc_int)
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{
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bfin_write_RTC_ICTL(bfin_read_RTC_ICTL() & rtc_int);
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}
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static void bfin_rtc_int_set_alarm(struct bfin_rtc *rtc)
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{
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/* Blackfin has different bits for whether the alarm is
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* more than 24 hours away.
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*/
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bfin_rtc_int_set(rtc->rtc_alarm.tm_yday == -1 ? RTC_ISTAT_ALARM : RTC_ISTAT_ALARM_DAY);
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}
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static int bfin_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
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{
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struct bfin_rtc *rtc = dev_get_drvdata(dev);
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dev_dbg_stamp(dev);
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if (enabled)
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bfin_rtc_int_set_alarm(rtc);
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else
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bfin_rtc_int_clear(~(RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY));
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return 0;
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}
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static int bfin_rtc_read_time(struct device *dev, struct rtc_time *tm)
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{
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struct bfin_rtc *rtc = dev_get_drvdata(dev);
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dev_dbg_stamp(dev);
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if (rtc->rtc_wrote_regs & 0x1)
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bfin_rtc_sync_pending(dev);
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rtc_bfin_to_tm(bfin_read_RTC_STAT(), tm);
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return 0;
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}
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static int bfin_rtc_set_time(struct device *dev, struct rtc_time *tm)
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{
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struct bfin_rtc *rtc = dev_get_drvdata(dev);
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int ret;
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unsigned long now;
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dev_dbg_stamp(dev);
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ret = rtc_tm_to_time(tm, &now);
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if (ret == 0) {
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if (rtc->rtc_wrote_regs & 0x1)
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bfin_rtc_sync_pending(dev);
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bfin_write_RTC_STAT(rtc_time_to_bfin(now));
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rtc->rtc_wrote_regs = 0x1;
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}
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return ret;
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}
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static int bfin_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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{
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struct bfin_rtc *rtc = dev_get_drvdata(dev);
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dev_dbg_stamp(dev);
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alrm->time = rtc->rtc_alarm;
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bfin_rtc_sync_pending(dev);
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alrm->enabled = !!(bfin_read_RTC_ICTL() & (RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY));
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return 0;
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}
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static int bfin_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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{
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struct bfin_rtc *rtc = dev_get_drvdata(dev);
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unsigned long rtc_alarm;
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dev_dbg_stamp(dev);
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if (rtc_tm_to_time(&alrm->time, &rtc_alarm))
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return -EINVAL;
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rtc->rtc_alarm = alrm->time;
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bfin_rtc_sync_pending(dev);
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bfin_write_RTC_ALARM(rtc_time_to_bfin(rtc_alarm));
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if (alrm->enabled)
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bfin_rtc_int_set_alarm(rtc);
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return 0;
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}
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static int bfin_rtc_proc(struct device *dev, struct seq_file *seq)
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{
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#define yesno(x) ((x) ? "yes" : "no")
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u16 ictl = bfin_read_RTC_ICTL();
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dev_dbg_stamp(dev);
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seq_printf(seq,
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"alarm_IRQ\t: %s\n"
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"wkalarm_IRQ\t: %s\n"
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"seconds_IRQ\t: %s\n",
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yesno(ictl & RTC_ISTAT_ALARM),
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yesno(ictl & RTC_ISTAT_ALARM_DAY),
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yesno(ictl & RTC_ISTAT_SEC));
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return 0;
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#undef yesno
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}
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static const struct rtc_class_ops bfin_rtc_ops = {
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.read_time = bfin_rtc_read_time,
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.set_time = bfin_rtc_set_time,
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.read_alarm = bfin_rtc_read_alarm,
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.set_alarm = bfin_rtc_set_alarm,
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.proc = bfin_rtc_proc,
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.alarm_irq_enable = bfin_rtc_alarm_irq_enable,
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};
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static int bfin_rtc_probe(struct platform_device *pdev)
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{
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struct bfin_rtc *rtc;
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struct device *dev = &pdev->dev;
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int ret;
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unsigned long timeout = jiffies + HZ;
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dev_dbg_stamp(dev);
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/* Allocate memory for our RTC struct */
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rtc = devm_kzalloc(dev, sizeof(*rtc), GFP_KERNEL);
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if (unlikely(!rtc))
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return -ENOMEM;
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platform_set_drvdata(pdev, rtc);
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device_init_wakeup(dev, 1);
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/* Register our RTC with the RTC framework */
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rtc->rtc_dev = devm_rtc_device_register(dev, pdev->name, &bfin_rtc_ops,
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THIS_MODULE);
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if (IS_ERR(rtc->rtc_dev))
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return PTR_ERR(rtc->rtc_dev);
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/* Grab the IRQ and init the hardware */
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ret = devm_request_irq(dev, IRQ_RTC, bfin_rtc_interrupt, 0,
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pdev->name, dev);
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if (unlikely(ret))
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dev_err(&pdev->dev,
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"unable to request IRQ; alarm won't work, "
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"and writes will be delayed\n");
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/* sometimes the bootloader touched things, but the write complete was not
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* enabled, so let's just do a quick timeout here since the IRQ will not fire ...
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*/
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while (bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_PENDING)
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if (time_after(jiffies, timeout))
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break;
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bfin_rtc_reset(dev, RTC_ISTAT_WRITE_COMPLETE);
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bfin_write_RTC_SWCNT(0);
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return 0;
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}
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static int bfin_rtc_remove(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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bfin_rtc_reset(dev, 0);
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return 0;
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}
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#ifdef CONFIG_PM_SLEEP
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static int bfin_rtc_suspend(struct device *dev)
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{
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dev_dbg_stamp(dev);
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if (device_may_wakeup(dev)) {
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enable_irq_wake(IRQ_RTC);
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bfin_rtc_sync_pending(dev);
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} else
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bfin_rtc_int_clear(0);
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return 0;
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}
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|
||||
static int bfin_rtc_resume(struct device *dev)
|
||||
{
|
||||
dev_dbg_stamp(dev);
|
||||
|
||||
if (device_may_wakeup(dev))
|
||||
disable_irq_wake(IRQ_RTC);
|
||||
|
||||
/*
|
||||
* Since only some of the RTC bits are maintained externally in the
|
||||
* Vbat domain, we need to wait for the RTC MMRs to be synced into
|
||||
* the core after waking up. This happens every RTC 1HZ. Once that
|
||||
* has happened, we can go ahead and re-enable the important write
|
||||
* complete interrupt event.
|
||||
*/
|
||||
while (!(bfin_read_RTC_ISTAT() & RTC_ISTAT_SEC))
|
||||
continue;
|
||||
bfin_rtc_int_set(RTC_ISTAT_WRITE_COMPLETE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static SIMPLE_DEV_PM_OPS(bfin_rtc_pm_ops, bfin_rtc_suspend, bfin_rtc_resume);
|
||||
|
||||
static struct platform_driver bfin_rtc_driver = {
|
||||
.driver = {
|
||||
.name = "rtc-bfin",
|
||||
.pm = &bfin_rtc_pm_ops,
|
||||
},
|
||||
.probe = bfin_rtc_probe,
|
||||
.remove = bfin_rtc_remove,
|
||||
};
|
||||
|
||||
module_platform_driver(bfin_rtc_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Blackfin On-Chip Real Time Clock Driver");
|
||||
MODULE_AUTHOR("Mike Frysinger <vapier@gentoo.org>");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_ALIAS("platform:rtc-bfin");
|
||||
Loading…
Reference in New Issue
Block a user