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arm64: dts: qcom: sdm845: Use UFS reset gpio instead of pinctrl

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We use a pinctrl "workaround" to toggle the UFS reset line. Now that UFS
controller can issue the reset, just specify the line as a GPIO and let
it be reset that way.

Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This commit is contained in:
Stephen Boyd 2019-08-29 22:59:23 -07:00 committed by Bjorn Andersson
parent 668c7603f0
commit 10e99d4754
1 changed files with 2 additions and 49 deletions
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51
arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi
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@ -701,9 +701,8 @@ ap_ts_i2c: &i2c14 {
&ufs_mem_hc {
status = "okay";
pinctrl-names = "init", "default";
pinctrl-0 = <&ufs_dev_reset_assert>;
pinctrl-1 = <&ufs_dev_reset_deassert>;
reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>;
vcc-supply = <&src_pp2950_l20a>;
vcc-max-microamp = <600000>;
@ -1258,52 +1257,6 @@ ap_ts_i2c: &i2c14 {
};
};
ufs_dev_reset_assert: ufs_dev_reset_assert {
config {
pins = "ufs_reset";
bias-pull-down; /* default: pull down */
/*
* UFS_RESET driver strengths are having
* different values/steps compared to typical
* GPIO drive strengths.
*
* Following table clarifies:
*
* HDRV value | UFS_RESET | Typical GPIO
* (dec) | (mA) | (mA)
* 0 | 0.8 | 2
* 1 | 1.55 | 4
* 2 | 2.35 | 6
* 3 | 3.1 | 8
* 4 | 3.9 | 10
* 5 | 4.65 | 12
* 6 | 5.4 | 14
* 7 | 6.15 | 16
*
* POR value for UFS_RESET HDRV is 3 which means
* 3.1mA and we want to use that. Hence just
* specify 8mA to "drive-strength" binding and
* that should result into writing 3 to HDRV
* field.
*/
drive-strength = <8>; /* default: 3.1 mA */
output-low; /* active low reset */
};
};
ufs_dev_reset_deassert: ufs_dev_reset_deassert {
config {
pins = "ufs_reset";
bias-pull-down; /* default: pull down */
/*
* default: 3.1 mA
* check comments under ufs_dev_reset_assert
*/
drive-strength = <8>;
output-high; /* active low reset */
};
};
ap_suspend_l_assert: ap_suspend_l_assert {
config {
pins = "gpio126";