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drm fixes for 5.18-rc7
amdgpu: - Disable ASPM for VI boards on ADL platforms - S0ix DCN3.1 display fix - Resume regression fix - Stable pstate fix i915: - fix for kernel memory corruption when running a lot of OpenCL tests in parallel -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEEKbZHaGwW9KfbeusDHTzWXnEhr4FAmJ9xWgACgkQDHTzWXnE hr7iIA/5ASqOx6jsjR4lcHKmbP/Ozh9H9DSi1dmqCrE6UKaZt934uVoqbFkZe27t znuXTlbAWRGsAEFMoFQaLkozQN4tuSEbFAJrw1gsD+/NXrjnRvL/8Vi8upJ1l3Zg npJxgD8hzMAfP0IWF3yYqehm2KvL+WHDREA24e7+CWOz7MZIlxQleXeLFOaDQ5DN 8o4KstAD2CNQZvR0mb8WqOfS6gvw5AgtAguT9i4xKpyGCTooHF69jK6HV9y93IvY pHm59QdXjDJeMSdk8TEHRP5KlSpyCaQqMuq5rraYUUW0IcnyfHFeO2jdsiWHUPnW qcOsQdAmTK9aNe1ZAJntAZbaLB5OYFbQiZyOjaquZJHZwf2n/lqEdZsnpB1Ehync Gg4Jo9vZSWC0nWvgyQ/I72CHf+V6BPyg3toM5eQRite/aZ3Fu1P+P1kVt4BGHxGQ wZDSU2r82IowZRmV2RWOUaa1j/z+MBzMoqDw+ToorBxBqw7eWNhmi/N5u6pMF7Cu P76bTZCHre/pOsIeQTRFE+eIqIxaUeuCae34aZQgdcp3aO3oVvTGxDDnuRRo51LU y+4dlPvECIdgaOED8qCq2d5H6+QD+MTUsQrACA5W/q/UKsmh9417EVVXjmiLQLSt bjJWzdTyi2+tIom1BDQmB4IfIY63oPNAklkd96Auzr8Mx0z1vzU= =Iyu0 -----END PGP SIGNATURE----- Merge tag 'drm-fixes-2022-05-13' of git://anongit.freedesktop.org/drm/drm Pull drm fixes from Dave Airlie: "Pretty quiet week on the fixes front, 4 amdgpu and one i915 fix. I think there might be a few misc fbdev ones outstanding, but I'll see if they are necessary and pass them on if so. amdgpu: - Disable ASPM for VI boards on ADL platforms - S0ix DCN3.1 display fix - Resume regression fix - Stable pstate fix i915: - fix for kernel memory corruption when running a lot of OpenCL tests in parallel" * tag 'drm-fixes-2022-05-13' of git://anongit.freedesktop.org/drm/drm: drm/amdgpu/ctx: only reset stable pstate if the user changed it (v2) Revert "drm/amd/pm: keep the BACO feature enabled for suspend" drm/i915: Fix race in __i915_vma_remove_closed drm/amd/display: undo clearing of z10 related function pointers drm/amdgpu: vi: disable ASPM on Intel Alder Lake based systems
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commit
10b4b67ab5
@ -296,6 +296,7 @@ static int amdgpu_ctx_set_stable_pstate(struct amdgpu_ctx *ctx,
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{
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struct amdgpu_device *adev = ctx->adev;
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enum amd_dpm_forced_level level;
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u32 current_stable_pstate;
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int r;
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mutex_lock(&adev->pm.stable_pstate_ctx_lock);
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@ -304,6 +305,10 @@ static int amdgpu_ctx_set_stable_pstate(struct amdgpu_ctx *ctx,
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goto done;
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}
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r = amdgpu_ctx_get_stable_pstate(ctx, ¤t_stable_pstate);
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if (r || (stable_pstate == current_stable_pstate))
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goto done;
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switch (stable_pstate) {
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case AMDGPU_CTX_STABLE_PSTATE_NONE:
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level = AMD_DPM_FORCED_LEVEL_AUTO;
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@ -81,6 +81,10 @@
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#include "mxgpu_vi.h"
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#include "amdgpu_dm.h"
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#if IS_ENABLED(CONFIG_X86)
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#include <asm/intel-family.h>
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#endif
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#define ixPCIE_LC_L1_PM_SUBSTATE 0x100100C6
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#define PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK 0x00000001L
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#define PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK 0x00000002L
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@ -1134,13 +1138,24 @@ static void vi_enable_aspm(struct amdgpu_device *adev)
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WREG32_PCIE(ixPCIE_LC_CNTL, data);
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}
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static bool aspm_support_quirk_check(void)
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{
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#if IS_ENABLED(CONFIG_X86)
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struct cpuinfo_x86 *c = &cpu_data(0);
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return !(c->x86 == 6 && c->x86_model == INTEL_FAM6_ALDERLAKE);
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#else
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return true;
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#endif
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}
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static void vi_program_aspm(struct amdgpu_device *adev)
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{
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u32 data, data1, orig;
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bool bL1SS = false;
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bool bClkReqSupport = true;
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if (!amdgpu_device_should_use_aspm(adev))
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if (!amdgpu_device_should_use_aspm(adev) || !aspm_support_quirk_check())
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return;
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if (adev->flags & AMD_IS_APU ||
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@ -153,9 +153,4 @@ void dcn31_hw_sequencer_construct(struct dc *dc)
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dc->hwss.init_hw = dcn20_fpga_init_hw;
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dc->hwseq->funcs.init_pipes = NULL;
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}
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if (dc->debug.disable_z10) {
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/*hw not support z10 or sw disable it*/
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dc->hwss.z10_restore = NULL;
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dc->hwss.z10_save_init = NULL;
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}
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}
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@ -1351,14 +1351,8 @@ static int smu_disable_dpms(struct smu_context *smu)
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{
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struct amdgpu_device *adev = smu->adev;
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int ret = 0;
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/*
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* TODO: (adev->in_suspend && !adev->in_s0ix) is added to pair
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* the workaround which always reset the asic in suspend.
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* It's likely that workaround will be dropped in the future.
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* Then the change here should be dropped together.
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*/
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bool use_baco = !smu->is_apu &&
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(((amdgpu_in_reset(adev) || (adev->in_suspend && !adev->in_s0ix)) &&
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((amdgpu_in_reset(adev) &&
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(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) ||
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((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev)));
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@ -1605,17 +1605,17 @@ void i915_vma_close(struct i915_vma *vma)
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static void __i915_vma_remove_closed(struct i915_vma *vma)
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{
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struct intel_gt *gt = vma->vm->gt;
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spin_lock_irq(>->closed_lock);
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list_del_init(&vma->closed_link);
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spin_unlock_irq(>->closed_lock);
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}
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void i915_vma_reopen(struct i915_vma *vma)
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{
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struct intel_gt *gt = vma->vm->gt;
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spin_lock_irq(>->closed_lock);
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if (i915_vma_is_closed(vma))
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__i915_vma_remove_closed(vma);
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spin_unlock_irq(>->closed_lock);
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}
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void i915_vma_release(struct kref *ref)
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@ -1641,6 +1641,7 @@ static void force_unbind(struct i915_vma *vma)
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static void release_references(struct i915_vma *vma)
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{
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struct drm_i915_gem_object *obj = vma->obj;
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struct intel_gt *gt = vma->vm->gt;
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GEM_BUG_ON(i915_vma_is_active(vma));
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@ -1650,7 +1651,9 @@ static void release_references(struct i915_vma *vma)
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rb_erase(&vma->obj_node, &obj->vma.tree);
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spin_unlock(&obj->vma.lock);
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spin_lock_irq(>->closed_lock);
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__i915_vma_remove_closed(vma);
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spin_unlock_irq(>->closed_lock);
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__i915_vma_put(vma);
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}
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