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imx: reorder mx2x.h
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
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@ -105,78 +105,78 @@
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(((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
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/* fixed interrupt numbers */
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#define MXC_INT_LCDC 61
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#define MXC_INT_SLCDC 60
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#define MXC_INT_EMMAPP 52
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#define MXC_INT_EMMAPRP 51
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#define MXC_INT_DMACH15 47
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#define MXC_INT_DMACH14 46
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#define MXC_INT_DMACH13 45
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#define MXC_INT_DMACH12 44
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#define MXC_INT_DMACH11 43
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#define MXC_INT_DMACH10 42
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#define MXC_INT_DMACH9 41
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#define MXC_INT_DMACH8 40
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#define MXC_INT_DMACH7 39
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#define MXC_INT_DMACH6 38
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#define MXC_INT_DMACH5 37
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#define MXC_INT_DMACH4 36
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#define MXC_INT_DMACH3 35
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#define MXC_INT_DMACH2 34
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#define MXC_INT_DMACH1 33
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#define MXC_INT_DMACH0 32
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#define MXC_INT_CSI 31
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#define MXC_INT_NANDFC 29
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#define MXC_INT_PCMCIA 28
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#define MXC_INT_WDOG 27
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#define MXC_INT_GPT1 26
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#define MXC_INT_GPT2 25
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#define MXC_INT_GPT3 24
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#define MXC_INT_GPT INT_GPT1
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#define MXC_INT_PWM 23
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#define MXC_INT_RTC 22
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#define MXC_INT_KPP 21
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#define MXC_INT_UART1 20
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#define MXC_INT_UART2 19
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#define MXC_INT_UART3 18
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#define MXC_INT_UART4 17
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#define MXC_INT_CSPI1 16
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#define MXC_INT_CSPI2 15
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#define MXC_INT_SSI1 14
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#define MXC_INT_SSI2 13
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#define MXC_INT_I2C 12
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#define MXC_INT_SDHC1 11
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#define MXC_INT_SDHC2 10
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#define MXC_INT_GPIO 8
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#define MXC_INT_CSPI3 6
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#define MXC_INT_GPIO 8
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#define MXC_INT_SDHC2 10
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#define MXC_INT_SDHC1 11
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#define MXC_INT_I2C 12
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#define MXC_INT_SSI2 13
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#define MXC_INT_SSI1 14
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#define MXC_INT_CSPI2 15
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#define MXC_INT_CSPI1 16
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#define MXC_INT_UART4 17
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#define MXC_INT_UART3 18
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#define MXC_INT_UART2 19
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#define MXC_INT_UART1 20
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#define MXC_INT_KPP 21
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#define MXC_INT_RTC 22
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#define MXC_INT_PWM 23
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#define MXC_INT_GPT INT_GPT1
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#define MXC_INT_GPT3 24
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#define MXC_INT_GPT2 25
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#define MXC_INT_GPT1 26
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#define MXC_INT_WDOG 27
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#define MXC_INT_PCMCIA 28
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#define MXC_INT_NANDFC 29
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#define MXC_INT_CSI 31
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#define MXC_INT_DMACH0 32
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#define MXC_INT_DMACH1 33
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#define MXC_INT_DMACH2 34
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#define MXC_INT_DMACH3 35
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#define MXC_INT_DMACH4 36
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#define MXC_INT_DMACH5 37
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#define MXC_INT_DMACH6 38
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#define MXC_INT_DMACH7 39
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#define MXC_INT_DMACH8 40
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#define MXC_INT_DMACH9 41
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#define MXC_INT_DMACH10 42
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#define MXC_INT_DMACH11 43
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#define MXC_INT_DMACH12 44
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#define MXC_INT_DMACH13 45
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#define MXC_INT_DMACH14 46
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#define MXC_INT_DMACH15 47
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#define MXC_INT_EMMAPRP 51
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#define MXC_INT_EMMAPP 52
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#define MXC_INT_SLCDC 60
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#define MXC_INT_LCDC 61
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/* fixed DMA request numbers */
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#define DMA_REQ_CSI_RX 31
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#define DMA_REQ_CSI_STAT 30
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#define DMA_REQ_UART1_TX 27
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#define DMA_REQ_UART1_RX 26
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#define DMA_REQ_UART2_TX 25
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#define DMA_REQ_UART2_RX 24
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#define DMA_REQ_UART3_TX 23
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#define DMA_REQ_UART3_RX 22
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#define DMA_REQ_UART4_TX 21
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#define DMA_REQ_UART4_RX 20
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#define DMA_REQ_CSPI1_TX 19
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#define DMA_REQ_CSPI1_RX 18
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#define DMA_REQ_CSPI2_TX 17
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#define DMA_REQ_CSPI2_RX 16
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#define DMA_REQ_SSI1_TX1 15
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#define DMA_REQ_SSI1_RX1 14
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#define DMA_REQ_SSI1_TX0 13
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#define DMA_REQ_SSI1_RX0 12
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#define DMA_REQ_SSI2_TX1 11
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#define DMA_REQ_SSI2_RX1 10
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#define DMA_REQ_SSI2_TX0 9
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#define DMA_REQ_SSI2_RX0 8
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#define DMA_REQ_SDHC1 7
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#define DMA_REQ_SDHC2 6
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#define DMA_REQ_EXT 3
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#define DMA_REQ_CSPI3_TX 2
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#define DMA_REQ_CSPI3_RX 1
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#define DMA_REQ_CSPI3_TX 2
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#define DMA_REQ_EXT 3
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#define DMA_REQ_SDHC2 6
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#define DMA_REQ_SDHC1 7
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#define DMA_REQ_SSI2_RX0 8
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#define DMA_REQ_SSI2_TX0 9
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#define DMA_REQ_SSI2_RX1 10
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#define DMA_REQ_SSI2_TX1 11
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#define DMA_REQ_SSI1_RX0 12
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#define DMA_REQ_SSI1_TX0 13
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#define DMA_REQ_SSI1_RX1 14
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#define DMA_REQ_SSI1_TX1 15
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#define DMA_REQ_CSPI2_RX 16
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#define DMA_REQ_CSPI2_TX 17
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#define DMA_REQ_CSPI1_RX 18
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#define DMA_REQ_CSPI1_TX 19
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#define DMA_REQ_UART4_RX 20
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#define DMA_REQ_UART4_TX 21
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#define DMA_REQ_UART3_RX 22
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#define DMA_REQ_UART3_TX 23
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#define DMA_REQ_UART2_RX 24
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#define DMA_REQ_UART2_TX 25
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#define DMA_REQ_UART1_RX 26
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#define DMA_REQ_UART1_TX 27
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#define DMA_REQ_CSI_STAT 30
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#define DMA_REQ_CSI_RX 31
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#endif /* __ASM_ARCH_MXC_MX2x_H__ */
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