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https://github.com/edk2-porting/linux-next.git
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ASoC: tas2552: Correct the PLL configuration
Do not restrict the sampling rate to 44.1/48KHz. The pll_clk clock should be (sampling rate * 512) in all cases. Correct the J.D calculation (the D part was incorrectly calculated). Restore PLL enable status after we are done with the configuration. Implement hardware constraint handling towards the pll_clkin: if D != 0 (in J.D) then 1.1MHz <= pll_clkin <= 9.2MHz needs to be checked. If the PLL setup does not met with this constraint, fall back to BCLK as reference clock, if BCLK fails, use the internal 1.8MHz clock. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Peter Ujfalusi
Mark Brown
parent
a571cb17ac
commit
1014f7eff9
@ -77,7 +77,9 @@ struct tas2552_data {
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struct gpio_desc *enable_gpio;
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unsigned char regs[TAS2552_VBAT_DATA];
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unsigned int pll_clkin;
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int pll_clk_id;
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unsigned int pdm_clk;
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int pdm_clk_id;
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unsigned int dai_fmt;
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unsigned int tdm_delay;
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@ -158,16 +160,90 @@ static void tas2552_sw_shutdown(struct tas2552_data *tas_data, int sw_shutdown)
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}
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#endif
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static int tas2552_setup_pll(struct snd_soc_codec *codec,
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struct snd_pcm_hw_params *params)
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{
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struct tas2552_data *tas2552 = dev_get_drvdata(codec->dev);
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bool bypass_pll = false;
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unsigned int pll_clk = params_rate(params) * 512;
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unsigned int pll_clkin = tas2552->pll_clkin;
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u8 pll_enable;
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if (!pll_clkin) {
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if (tas2552->pll_clk_id != TAS2552_PLL_CLKIN_BCLK)
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return -EINVAL;
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pll_clkin = snd_soc_params_to_bclk(params);
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pll_clkin += tas2552->tdm_delay;
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}
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pll_enable = snd_soc_read(codec, TAS2552_CFG_2) & TAS2552_PLL_ENABLE;
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snd_soc_update_bits(codec, TAS2552_CFG_2, TAS2552_PLL_ENABLE, 0);
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if (pll_clkin == pll_clk)
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bypass_pll = true;
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if (bypass_pll) {
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/* By pass the PLL configuration */
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snd_soc_update_bits(codec, TAS2552_PLL_CTRL_2,
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TAS2552_PLL_BYPASS, TAS2552_PLL_BYPASS);
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} else {
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/* Fill in the PLL control registers for J & D
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* pll_clk = (.5 * pll_clkin * J.D) / 2^p
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* Need to fill in J and D here based on incoming freq
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*/
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unsigned int d;
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u8 j;
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u8 pll_sel = (tas2552->pll_clk_id << 3) & TAS2552_PLL_SRC_MASK;
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u8 p = snd_soc_read(codec, TAS2552_PLL_CTRL_1);
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p = (p >> 7);
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recalc:
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j = (pll_clk * 2 * (1 << p)) / pll_clkin;
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d = (pll_clk * 2 * (1 << p)) % pll_clkin;
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d /= (pll_clkin / 10000);
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if (d && (pll_clkin < 512000 || pll_clkin > 9200000)) {
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if (tas2552->pll_clk_id == TAS2552_PLL_CLKIN_BCLK) {
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pll_clkin = 1800000;
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pll_sel = (TAS2552_PLL_CLKIN_1_8_FIXED << 3) &
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TAS2552_PLL_SRC_MASK;
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} else {
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pll_clkin = snd_soc_params_to_bclk(params);
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pll_clkin += tas2552->tdm_delay;
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pll_sel = (TAS2552_PLL_CLKIN_BCLK << 3) &
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TAS2552_PLL_SRC_MASK;
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}
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goto recalc;
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}
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snd_soc_update_bits(codec, TAS2552_CFG_1, TAS2552_PLL_SRC_MASK,
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pll_sel);
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snd_soc_update_bits(codec, TAS2552_PLL_CTRL_1,
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TAS2552_PLL_J_MASK, j);
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/* Will clear the PLL_BYPASS bit */
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snd_soc_write(codec, TAS2552_PLL_CTRL_2,
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TAS2552_PLL_D_UPPER(d));
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snd_soc_write(codec, TAS2552_PLL_CTRL_3,
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TAS2552_PLL_D_LOWER(d));
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}
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/* Restore PLL status */
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snd_soc_update_bits(codec, TAS2552_CFG_2, TAS2552_PLL_ENABLE,
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pll_enable);
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return 0;
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}
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static int tas2552_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct snd_soc_codec *codec = dai->codec;
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struct tas2552_data *tas2552 = dev_get_drvdata(codec->dev);
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int sample_rate, pll_clk;
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int d;
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int cpf;
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u8 p, j;
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u8 ser_ctrl1_reg, wclk_rate;
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switch (params_width(params)) {
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@ -245,49 +321,7 @@ static int tas2552_hw_params(struct snd_pcm_substream *substream,
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snd_soc_update_bits(codec, TAS2552_CFG_3, TAS2552_WCLK_FREQ_MASK,
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wclk_rate);
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if (!tas2552->pll_clkin)
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return -EINVAL;
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snd_soc_update_bits(codec, TAS2552_CFG_2, TAS2552_PLL_ENABLE, 0);
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if (tas2552->pll_clkin == TAS2552_245MHZ_CLK ||
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tas2552->pll_clkin == TAS2552_225MHZ_CLK) {
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/* By pass the PLL configuration */
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snd_soc_update_bits(codec, TAS2552_PLL_CTRL_2,
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TAS2552_PLL_BYPASS_MASK,
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TAS2552_PLL_BYPASS);
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} else {
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/* Fill in the PLL control registers for J & D
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* PLL_CLK = (.5 * freq * J.D) / 2^p
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* Need to fill in J and D here based on incoming freq
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*/
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p = snd_soc_read(codec, TAS2552_PLL_CTRL_1);
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p = (p >> 7);
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sample_rate = params_rate(params);
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if (sample_rate == 48000)
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pll_clk = TAS2552_245MHZ_CLK;
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else if (sample_rate == 44100)
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pll_clk = TAS2552_225MHZ_CLK;
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else {
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dev_vdbg(codec->dev, "Substream sample rate is not found %i\n",
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params_rate(params));
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return -EINVAL;
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}
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j = (pll_clk * 2 * (1 << p)) / tas2552->pll_clkin;
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d = (pll_clk * 2 * (1 << p)) % tas2552->pll_clkin;
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snd_soc_update_bits(codec, TAS2552_PLL_CTRL_1,
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TAS2552_PLL_J_MASK, j);
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snd_soc_write(codec, TAS2552_PLL_CTRL_2,
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(d >> 7) & TAS2552_PLL_D_UPPER_MASK);
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snd_soc_write(codec, TAS2552_PLL_CTRL_3,
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d & TAS2552_PLL_D_LOWER_MASK);
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}
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return 0;
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return tas2552_setup_pll(codec, params);
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}
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#define TAS2552_DAI_FMT_MASK (TAS2552_BCLKDIR | \
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@ -370,12 +404,21 @@ static int tas2552_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
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switch (clk_id) {
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case TAS2552_PLL_CLKIN_MCLK:
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case TAS2552_PLL_CLKIN_BCLK:
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case TAS2552_PLL_CLKIN_IVCLKIN:
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if (freq < 512000 || freq > 24576000) {
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/* out of range PLL_CLKIN, fall back to use BCLK */
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dev_warn(codec->dev, "Out of range PLL_CLKIN: %u\n",
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freq);
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clk_id = TAS2552_PLL_CLKIN_BCLK;
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freq = 0;
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}
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/* fall through */
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case TAS2552_PLL_CLKIN_BCLK:
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case TAS2552_PLL_CLKIN_1_8_FIXED:
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mask = TAS2552_PLL_SRC_MASK;
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val = (clk_id << 3) & mask; /* bit 4:5 in the register */
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reg = TAS2552_CFG_1;
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tas2552->pll_clk_id = clk_id;
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tas2552->pll_clkin = freq;
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break;
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case TAS2552_PDM_CLK_PLL:
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@ -385,6 +428,7 @@ static int tas2552_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
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mask = TAS2552_PDM_CLK_SEL_MASK;
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val = (clk_id >> 1) & mask; /* bit 0:1 in the register */
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reg = TAS2552_PDM_CFG;
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tas2552->pdm_clk_id = clk_id;
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tas2552->pdm_clk = freq;
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break;
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default:
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@ -128,12 +128,9 @@
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#define TAS2552_APT_THRESH_2_1_7 (0x11 << 2)
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/* PLL Control Register */
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#define TAS2552_245MHZ_CLK 24576000
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#define TAS2552_225MHZ_CLK 22579200
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#define TAS2552_PLL_J_MASK 0x7f
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#define TAS2552_PLL_D_UPPER_MASK 0x3f
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#define TAS2552_PLL_D_LOWER_MASK 0xff
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#define TAS2552_PLL_BYPASS_MASK 0x80
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#define TAS2552_PLL_BYPASS 0x80
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#define TAS2552_PLL_J_MASK 0x7f
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#define TAS2552_PLL_D_UPPER(x) (((x) >> 8) & 0x3f)
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#define TAS2552_PLL_D_LOWER(x) ((x) & 0xff)
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#define TAS2552_PLL_BYPASS (1 << 7)
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#endif
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