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https://github.com/edk2-porting/linux-next.git
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KVM: x86 emulator: switch src decode to decode_operand()
Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
This commit is contained in:
Avi Kivity
parent
5217973ef8
commit
0fe5912884
@ -44,8 +44,15 @@
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#define OpImmByte 10ull /* 8-bit sign extended immediate */
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#define OpOne 11ull /* Implied 1 */
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#define OpImm 12ull /* Sign extended immediate */
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#define OpMem16 13ull /* Memory operand (16-bit). */
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#define OpMem32 14ull /* Memory operand (32-bit). */
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#define OpImmU 15ull /* Immediate operand, zero extended */
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#define OpSI 16ull /* SI/ESI/RSI */
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#define OpImmFAddr 17ull /* Immediate far address */
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#define OpMemFAddr 18ull /* Far address in memory */
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#define OpImmU16 19ull /* Immediate operand, 16 bits, zero extended */
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#define OpBits 4 /* Width of operand field */
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#define OpBits 5 /* Width of operand field */
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#define OpMask ((1ull << OpBits) - 1)
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/*
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@ -71,23 +78,24 @@
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#define DstDX (OpDX << DstShift)
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#define DstMask (OpMask << DstShift)
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/* Source operand type. */
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#define SrcNone (0<<5) /* No source operand. */
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#define SrcReg (1<<5) /* Register operand. */
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#define SrcMem (2<<5) /* Memory operand. */
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#define SrcMem16 (3<<5) /* Memory operand (16-bit). */
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#define SrcMem32 (4<<5) /* Memory operand (32-bit). */
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#define SrcImm (5<<5) /* Immediate operand. */
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#define SrcImmByte (6<<5) /* 8-bit sign-extended immediate operand. */
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#define SrcOne (7<<5) /* Implied '1' */
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#define SrcImmUByte (8<<5) /* 8-bit unsigned immediate operand. */
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#define SrcImmU (9<<5) /* Immediate operand, unsigned */
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#define SrcSI (0xa<<5) /* Source is in the DS:RSI */
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#define SrcImmFAddr (0xb<<5) /* Source is immediate far address */
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#define SrcMemFAddr (0xc<<5) /* Source is far address in memory */
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#define SrcAcc (0xd<<5) /* Source Accumulator */
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#define SrcImmU16 (0xe<<5) /* Immediate operand, unsigned, 16 bits */
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#define SrcDX (0xf<<5) /* Source is in DX register */
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#define SrcMask (0xf<<5)
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#define SrcShift 6
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#define SrcNone (OpNone << SrcShift)
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#define SrcReg (OpReg << SrcShift)
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#define SrcMem (OpMem << SrcShift)
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#define SrcMem16 (OpMem16 << SrcShift)
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#define SrcMem32 (OpMem32 << SrcShift)
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#define SrcImm (OpImm << SrcShift)
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#define SrcImmByte (OpImmByte << SrcShift)
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#define SrcOne (OpOne << SrcShift)
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#define SrcImmUByte (OpImmUByte << SrcShift)
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#define SrcImmU (OpImmU << SrcShift)
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#define SrcSI (OpSI << SrcShift)
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#define SrcImmFAddr (OpImmFAddr << SrcShift)
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#define SrcMemFAddr (OpMemFAddr << SrcShift)
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#define SrcAcc (OpAcc << SrcShift)
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#define SrcImmU16 (OpImmU16 << SrcShift)
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#define SrcDX (OpDX << SrcShift)
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#define SrcMask (OpMask << SrcShift)
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#define BitOp (1<<11)
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#define MemAbs (1<<12) /* Memory operand is absolute displacement */
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#define String (1<<13) /* String instruction (rep capable) */
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@ -3354,13 +3362,14 @@ static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
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break;
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case OpMem:
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case OpMem64:
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if (d == OpMem64)
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ctxt->memop.bytes = 8;
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else
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ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
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mem_common:
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*op = ctxt->memop;
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ctxt->memopp = op;
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if (d == OpMem64)
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op->bytes = 8;
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else
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op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
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if (ctxt->d & BitOp)
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if ((ctxt->d & BitOp) && op == &ctxt->dst)
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fetch_bit_operand(ctxt);
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op->orig_val = op->val;
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break;
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@ -3399,6 +3408,35 @@ static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
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case OpImm:
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rc = decode_imm(ctxt, op, imm_size(ctxt), true);
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break;
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case OpMem16:
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ctxt->memop.bytes = 2;
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goto mem_common;
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case OpMem32:
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ctxt->memop.bytes = 4;
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goto mem_common;
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case OpImmU16:
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rc = decode_imm(ctxt, op, 2, false);
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break;
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case OpImmU:
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rc = decode_imm(ctxt, op, imm_size(ctxt), false);
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break;
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case OpSI:
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op->type = OP_MEM;
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op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
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op->addr.mem.ea =
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register_address(ctxt, ctxt->regs[VCPU_REGS_RSI]);
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op->addr.mem.seg = seg_override(ctxt);
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op->val = 0;
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break;
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case OpImmFAddr:
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op->type = OP_IMM;
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op->addr.mem.ea = ctxt->_eip;
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op->bytes = ctxt->op_bytes + 2;
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insn_fetch_arr(op->valptr, op->bytes, ctxt);
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break;
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case OpMemFAddr:
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ctxt->memop.bytes = ctxt->op_bytes + 2;
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goto mem_common;
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case OpImplicit:
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/* Special instructions do their own operand decoding. */
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default:
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@ -3597,75 +3635,7 @@ done_prefixes:
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* Decode and fetch the source operand: register, memory
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* or immediate.
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*/
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switch (ctxt->d & SrcMask) {
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case SrcNone:
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break;
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case SrcReg:
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decode_register_operand(ctxt, &ctxt->src, 0);
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break;
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case SrcMem16:
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ctxt->memop.bytes = 2;
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goto srcmem_common;
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case SrcMem32:
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ctxt->memop.bytes = 4;
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goto srcmem_common;
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case SrcMem:
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ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
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srcmem_common:
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ctxt->src = ctxt->memop;
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ctxt->memopp = &ctxt->src;
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break;
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case SrcImmU16:
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rc = decode_imm(ctxt, &ctxt->src, 2, false);
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break;
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case SrcImm:
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rc = decode_imm(ctxt, &ctxt->src, imm_size(ctxt), true);
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break;
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case SrcImmU:
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rc = decode_imm(ctxt, &ctxt->src, imm_size(ctxt), false);
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break;
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case SrcImmByte:
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rc = decode_imm(ctxt, &ctxt->src, 1, true);
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break;
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case SrcImmUByte:
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rc = decode_imm(ctxt, &ctxt->src, 1, false);
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break;
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case SrcAcc:
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ctxt->src.type = OP_REG;
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ctxt->src.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
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ctxt->src.addr.reg = &ctxt->regs[VCPU_REGS_RAX];
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fetch_register_operand(&ctxt->src);
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break;
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case SrcOne:
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ctxt->src.bytes = 1;
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ctxt->src.val = 1;
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break;
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case SrcSI:
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ctxt->src.type = OP_MEM;
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ctxt->src.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
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ctxt->src.addr.mem.ea =
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register_address(ctxt, ctxt->regs[VCPU_REGS_RSI]);
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ctxt->src.addr.mem.seg = seg_override(ctxt);
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ctxt->src.val = 0;
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break;
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case SrcImmFAddr:
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ctxt->src.type = OP_IMM;
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ctxt->src.addr.mem.ea = ctxt->_eip;
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ctxt->src.bytes = ctxt->op_bytes + 2;
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insn_fetch_arr(ctxt->src.valptr, ctxt->src.bytes, ctxt);
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break;
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case SrcMemFAddr:
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ctxt->memop.bytes = ctxt->op_bytes + 2;
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goto srcmem_common;
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break;
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case SrcDX:
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ctxt->src.type = OP_REG;
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ctxt->src.bytes = 2;
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ctxt->src.addr.reg = &ctxt->regs[VCPU_REGS_RDX];
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fetch_register_operand(&ctxt->src);
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break;
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}
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rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
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if (rc != X86EMUL_CONTINUE)
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goto done;
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