mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-23 04:34:11 +08:00
MIPS: OCTEON: Get rid of CONFIG_CAVIUM_OCTEON_HW_FIX_UNALIGNED
When you turn it off, the kernel is unusable, so get rid of the option and always allow unaligned access. The Octeon specific memcpy intentionally does unaligned accesses and it must not fault. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5303/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
parent
02a49d5144
commit
0ec315121c
arch/mips
@ -23,17 +23,6 @@ config CAVIUM_OCTEON_2ND_KERNEL
|
||||
with this option to be run at the same time as one built without this
|
||||
option.
|
||||
|
||||
config CAVIUM_OCTEON_HW_FIX_UNALIGNED
|
||||
bool "Enable hardware fixups of unaligned loads and stores"
|
||||
default "y"
|
||||
help
|
||||
Configure the Octeon hardware to automatically fix unaligned loads
|
||||
and stores. Normally unaligned accesses are fixed using a kernel
|
||||
exception handler. This option enables the hardware automatic fixups,
|
||||
which requires only an extra 3 cycles. Disable this option if you
|
||||
are running code that relies on address exceptions on unaligned
|
||||
accesses.
|
||||
|
||||
config CAVIUM_OCTEON_CVMSEG_SIZE
|
||||
int "Number of L1 cache lines reserved for CVMSEG memory"
|
||||
range 0 54
|
||||
|
@ -34,15 +34,10 @@
|
||||
ori v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
|
||||
dmtc0 v0, CP0_CVMMEMCTL_REG # Write the cavium mem control register
|
||||
dmfc0 v0, CP0_CVMCTL_REG # Read the cavium control register
|
||||
#ifdef CONFIG_CAVIUM_OCTEON_HW_FIX_UNALIGNED
|
||||
# Disable unaligned load/store support but leave HW fixup enabled
|
||||
# Needed for octeon specific memcpy
|
||||
or v0, v0, 0x5001
|
||||
xor v0, v0, 0x1001
|
||||
#else
|
||||
# Disable unaligned load/store and HW fixup support
|
||||
or v0, v0, 0x5001
|
||||
xor v0, v0, 0x5001
|
||||
#endif
|
||||
# Read the processor ID register
|
||||
mfc0 v1, CP0_PRID_REG
|
||||
# Disable instruction prefetching (Octeon Pass1 errata)
|
||||
|
Loading…
Reference in New Issue
Block a user