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drm/nouveau/disp/nv50-: port OR manual sink detection to nvkm_ior

Browse Source 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2017-05-19 23:59:35 +10:00
parent 9c5753bc70
commit 0df1824662
17 changed files with 39 additions and 79 deletions
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1
drivers/gpu/drm/nouveau/nvkm/engine/disp/dacgf119.c
View File

@ -43,6 +43,7 @@ static const struct nvkm_ior_func
gf119_dac = {
.state = gf119_dac_state,
.power = nv50_dac_power,
.sense = nv50_dac_sense,
};
int

45
drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c
View File

@ -22,15 +22,10 @@
* Authors: Ben Skeggs
*/
#include "ior.h"
#include "nv50.h"
#include "outp.h"
#include <core/client.h>
#include <subdev/timer.h>
#include <nvif/cl5070.h>
#include <nvif/unpack.h>
static const struct nvkm_output_func
nv50_dac_output_func = {
};
@ -44,50 +39,23 @@ nv50_dac_output_new(struct nvkm_disp *disp, int index,
}
int
nv50_dac_sense(NV50_DISP_MTHD_V1)
nv50_dac_sense(struct nvkm_ior *dac, u32 loadval)
{
struct nvkm_subdev *subdev = &disp->base.engine.subdev;
struct nvkm_device *device = subdev->device;
union {
struct nv50_disp_dac_load_v0 v0;
} *args = data;
const u32 doff = outp->or * 0x800;
u32 loadval;
int ret = -ENOSYS;
struct nvkm_device *device = dac->disp->engine.subdev.device;
const u32 doff = nv50_ior_base(dac);
nvif_ioctl(object, "disp dac load size %d\n", size);
if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
nvif_ioctl(object, "disp dac load vers %d data %08x\n",
args->v0.version, args->v0.data);
if (args->v0.data & 0xfff00000)
return -EINVAL;
loadval = args->v0.data;
} else
return ret;
nvkm_mask(device, 0x61a004 + doff, 0x807f0000, 0x80150000);
nvkm_msec(device, 2000,
if (!(nvkm_rd32(device, 0x61a004 + doff) & 0x80000000))
break;
);
dac->func->power(dac, false, true, false, false, false);
nvkm_wr32(device, 0x61a00c + doff, 0x00100000 | loadval);
mdelay(9);
udelay(500);
loadval = nvkm_mask(device, 0x61a00c + doff, 0xffffffff, 0x00000000);
nvkm_mask(device, 0x61a004 + doff, 0x807f0000, 0x80550000);
nvkm_msec(device, 2000,
if (!(nvkm_rd32(device, 0x61a004 + doff) & 0x80000000))
break;
);
nvkm_debug(subdev, "DAC%d sense: %08x\n", outp->or, loadval);
dac->func->power(dac, false, false, false, false, false);
if (!(loadval & 0x80000000))
return -ETIMEDOUT;
args->v0.load = (loadval & 0x38000000) >> 27;
return 0;
return (loadval & 0x38000000) >> 27;
}
static void
@ -139,6 +107,7 @@ static const struct nvkm_ior_func
nv50_dac = {
.state = nv50_dac_state,
.power = nv50_dac_power,
.sense = nv50_dac_sense,
};
int

4
drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c
View File

@ -38,9 +38,7 @@ g84_disp = {
.outp.internal.lvds = nv50_sor_output_new,
.outp.external.tmds = nv50_pior_output_new,
.outp.external.dp = nv50_pior_dp_new,
.dac.nr = 3,
.dac.new = nv50_dac_new,
.dac.sense = nv50_dac_sense,
.dac = { .nr = 3, .new = nv50_dac_new },
.sor.nr = 2,
.sor.new = g84_sor_new,
.sor.hdmi = g84_hdmi_ctrl,

4
drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c
View File

@ -39,9 +39,7 @@ g94_disp = {
.outp.internal.dp = g94_sor_dp_new,
.outp.external.tmds = nv50_pior_output_new,
.outp.external.dp = nv50_pior_dp_new,
.dac.nr = 3,
.dac.new = nv50_dac_new,
.dac.sense = nv50_dac_sense,
.dac = { .nr = 3, .new = nv50_dac_new },
.sor.nr = 4,
.sor.new = g94_sor_new,
.sor.hdmi = g84_hdmi_ctrl,

4
drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.c
View File

@ -506,9 +506,7 @@ gf119_disp = {
.outp.internal.tmds = nv50_sor_output_new,
.outp.internal.lvds = nv50_sor_output_new,
.outp.internal.dp = gf119_sor_dp_new,
.dac.nr = 3,
.dac.new = gf119_dac_new,
.dac.sense = nv50_dac_sense,
.dac = { .nr = 3, .new = gf119_dac_new },
.sor.nr = 4,
.sor.new = gf119_sor_new,
.sor.hda_eld = gf119_hda_eld,

4
drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c
View File

@ -38,9 +38,7 @@ gk104_disp = {
.outp.internal.tmds = nv50_sor_output_new,
.outp.internal.lvds = nv50_sor_output_new,
.outp.internal.dp = gf119_sor_dp_new,
.dac.nr = 3,
.dac.new = gf119_dac_new,
.dac.sense = nv50_dac_sense,
.dac = { .nr = 3, .new = gf119_dac_new },
.sor.nr = 4,
.sor.new = gk104_sor_new,
.sor.hda_eld = gf119_hda_eld,

4
drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.c
View File

@ -38,9 +38,7 @@ gk110_disp = {
.outp.internal.tmds = nv50_sor_output_new,
.outp.internal.lvds = nv50_sor_output_new,
.outp.internal.dp = gf119_sor_dp_new,
.dac.nr = 3,
.dac.new = gf119_dac_new,
.dac.sense = nv50_dac_sense,
.dac = { .nr = 3, .new = gf119_dac_new },
.sor.nr = 4,
.sor.new = gk104_sor_new,
.sor.hda_eld = gf119_hda_eld,

4
drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c
View File

@ -38,9 +38,7 @@ gm107_disp = {
.outp.internal.tmds = nv50_sor_output_new,
.outp.internal.lvds = nv50_sor_output_new,
.outp.internal.dp = gm107_sor_dp_new,
.dac.nr = 3,
.dac.new = gf119_dac_new,
.dac.sense = nv50_dac_sense,
.dac = { .nr = 3, .new = gf119_dac_new },
.sor.nr = 4,
.sor.new = gm107_sor_new,
.sor.hda_eld = gf119_hda_eld,

4
drivers/gpu/drm/nouveau/nvkm/engine/disp/gm200.c
View File

@ -38,9 +38,7 @@ gm200_disp = {
.outp.internal.tmds = nv50_sor_output_new,
.outp.internal.lvds = nv50_sor_output_new,
.outp.internal.dp = gm200_sor_dp_new,
.dac.nr = 3,
.dac.new = gf119_dac_new,
.dac.sense = nv50_dac_sense,
.dac = { .nr = 3, .new = gf119_dac_new },
.sor.nr = 4,
.sor.new = gm200_sor_new,
.sor.hda_eld = gf119_hda_eld,

4
drivers/gpu/drm/nouveau/nvkm/engine/disp/gt200.c
View File

@ -38,9 +38,7 @@ gt200_disp = {
.outp.internal.lvds = nv50_sor_output_new,
.outp.external.tmds = nv50_pior_output_new,
.outp.external.dp = nv50_pior_dp_new,
.dac.nr = 3,
.dac.new = nv50_dac_new,
.dac.sense = nv50_dac_sense,
.dac = { .nr = 3, .new = nv50_dac_new },
.sor.nr = 2,
.sor.new = g84_sor_new,
.sor.hdmi = g84_hdmi_ctrl,

4
drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c
View File

@ -39,9 +39,7 @@ gt215_disp = {
.outp.internal.dp = g94_sor_dp_new,
.outp.external.tmds = nv50_pior_output_new,
.outp.external.dp = nv50_pior_dp_new,
.dac.nr = 3,
.dac.new = nv50_dac_new,
.dac.sense = nv50_dac_sense,
.dac = { .nr = 3, .new = nv50_dac_new },
.sor.nr = 4,
.sor.new = gt215_sor_new,
.sor.hda_eld = gt215_hda_eld,

2
drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h
View File

@ -42,6 +42,7 @@ struct nvkm_ior_func {
void (*state)(struct nvkm_ior *, struct nvkm_ior_state *);
void (*power)(struct nvkm_ior *, bool normal, bool pu,
bool data, bool vsync, bool hsync);
int (*sense)(struct nvkm_ior *, u32 loadval);
};
int nvkm_ior_new_(const struct nvkm_ior_func *func, struct nvkm_disp *,
@ -56,6 +57,7 @@ nv50_ior_base(struct nvkm_ior *ior)
}
void nv50_dac_power(struct nvkm_ior *, bool, bool, bool, bool, bool);
int nv50_dac_sense(struct nvkm_ior *, u32);
void nv50_sor_state(struct nvkm_ior *, struct nvkm_ior_state *);
void nv50_sor_power(struct nvkm_ior *, bool, bool, bool, bool, bool);

4
drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp77.c
View File

@ -37,9 +37,7 @@ mcp77_disp = {
.outp.internal.dp = g94_sor_dp_new,
.outp.external.tmds = nv50_pior_output_new,
.outp.external.dp = nv50_pior_dp_new,
.dac.nr = 3,
.dac.new = nv50_dac_new,
.dac.sense = nv50_dac_sense,
.dac = { .nr = 3, .new = nv50_dac_new },
.sor.nr = 4,
.sor.new = mcp77_sor_new,
.sor.hdmi = g84_hdmi_ctrl,

4
drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp89.c
View File

@ -37,9 +37,7 @@ mcp89_disp = {
.outp.internal.dp = g94_sor_dp_new,
.outp.external.tmds = nv50_pior_output_new,
.outp.external.dp = nv50_pior_dp_new,
.dac.nr = 3,
.dac.new = nv50_dac_new,
.dac.sense = nv50_dac_sense,
.dac = { .nr = 3, .new = nv50_dac_new },
.sor.nr = 4,
.sor.new = mcp89_sor_new,
.sor.hda_eld = gt215_hda_eld,

4
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c
View File

@ -844,9 +844,7 @@ nv50_disp = {
.outp.internal.lvds = nv50_sor_output_new,
.outp.external.tmds = nv50_pior_output_new,
.outp.external.dp = nv50_pior_dp_new,
.dac.nr = 3,
.dac.new = nv50_dac_new,
.dac.sense = nv50_dac_sense,
.dac = { .nr = 3, .new = nv50_dac_new },
.sor = { .nr = 2, .new = nv50_sor_new },
.pior = { .nr = 3, .new = nv50_pior_new },
};

3
drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h
View File

@ -31,8 +31,6 @@ struct nv50_disp {
void nv50_disp_super_1(struct nv50_disp *);
int nv50_dac_sense(NV50_DISP_MTHD_V1);
int gt215_hda_eld(NV50_DISP_MTHD_V1);
int gf119_hda_eld(NV50_DISP_MTHD_V1);
@ -80,7 +78,6 @@ struct nv50_disp_func {
struct {
int nr;
int (*new)(struct nvkm_disp *, int id);
int (*sense)(NV50_DISP_MTHD_V1);
} dac;
struct {

19
drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c
View File

@ -95,8 +95,23 @@ nv50_disp_root_mthd_(struct nvkm_object *object, u32 mthd, void *data, u32 size)
}
switch (mthd * !!outp) {
case NV50_DISP_MTHD_V1_DAC_LOAD:
return func->dac.sense(object, disp, data, size, hidx, outp);
case NV50_DISP_MTHD_V1_DAC_LOAD: {
union {
struct nv50_disp_dac_load_v0 v0;
} *args = data;
int ret = -ENOSYS;
if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
if (args->v0.data & 0xfff00000)
return -EINVAL;
ret = outp->ior->func->sense(outp->ior, args->v0.data);
if (ret < 0)
return ret;
args->v0.load = ret;
return 0;
} else
return ret;
}
break;
case NV50_DISP_MTHD_V1_SOR_HDA_ELD:
if (!func->sor.hda_eld)
return -ENODEV;