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irqchip: mips-gic: Convert remaining local reg access to new accessors
Convert the remaining accesses to registers in the GIC VP-local & VP-other register blocks to use the new accessor functions provided by asm/mips-gic.h, resulting in code which is often shorter & easier to read. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17036/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Paul Burton
Ralf Baechle
parent
9da3c64589
commit
0d0cf58cd6
@ -45,42 +45,6 @@ DECLARE_BITMAP(ipi_available, GIC_MAX_INTRS);
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static void __gic_irq_dispatch(void);
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static inline u32 gic_read32(unsigned int reg)
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{
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return __raw_readl(mips_gic_base + reg);
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}
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static inline u64 gic_read64(unsigned int reg)
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{
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return __raw_readq(mips_gic_base + reg);
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}
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static inline unsigned long gic_read(unsigned int reg)
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{
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if (!mips_cm_is64)
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return gic_read32(reg);
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else
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return gic_read64(reg);
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}
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static inline void gic_write32(unsigned int reg, u32 val)
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{
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return __raw_writel(val, mips_gic_base + reg);
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}
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static inline void gic_write64(unsigned int reg, u64 val)
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{
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return __raw_writeq(val, mips_gic_base + reg);
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}
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static inline void gic_write(unsigned int reg, unsigned long val)
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{
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if (!mips_cm_is64)
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return gic_write32(reg, (u32)val);
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else
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return gic_write64(reg, (u64)val);
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}
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static bool gic_local_irq_is_routable(int intr)
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{
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u32 vpe_ctl;
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@ -89,17 +53,17 @@ static bool gic_local_irq_is_routable(int intr)
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if (cpu_has_veic)
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return true;
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vpe_ctl = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_CTL));
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vpe_ctl = read_gic_vl_ctl();
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switch (intr) {
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case GIC_LOCAL_INT_TIMER:
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return vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK;
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return vpe_ctl & GIC_VX_CTL_TIMER_ROUTABLE;
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case GIC_LOCAL_INT_PERFCTR:
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return vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK;
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return vpe_ctl & GIC_VX_CTL_PERFCNT_ROUTABLE;
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case GIC_LOCAL_INT_FDC:
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return vpe_ctl & GIC_VPE_CTL_FDC_RTBL_MSK;
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return vpe_ctl & GIC_VX_CTL_FDC_ROUTABLE;
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case GIC_LOCAL_INT_SWINT0:
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case GIC_LOCAL_INT_SWINT1:
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return vpe_ctl & GIC_VPE_CTL_SWINT_RTBL_MSK;
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return vpe_ctl & GIC_VX_CTL_SWINT_ROUTABLE;
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default:
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return true;
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}
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@ -111,8 +75,7 @@ static void gic_bind_eic_interrupt(int irq, int set)
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irq -= GIC_PIN_TO_VEC_OFFSET;
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/* Set irq to use shadow set */
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gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_EIC_SHADOW_SET_BASE) +
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GIC_VPE_EIC_SS(irq), set);
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write_gic_vl_eic_shadow_set(irq, set);
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}
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static void gic_send_ipi(struct irq_data *d, unsigned int cpu)
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@ -371,8 +334,7 @@ static void gic_mask_local_irq_all_vpes(struct irq_data *d)
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spin_lock_irqsave(&gic_lock, flags);
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for (i = 0; i < gic_vpes; i++) {
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gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR),
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mips_cm_vp_id(i));
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write_gic_vl_other(mips_cm_vp_id(i));
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write_gic_vo_rmask(BIT(intr));
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}
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spin_unlock_irqrestore(&gic_lock, flags);
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@ -386,8 +348,7 @@ static void gic_unmask_local_irq_all_vpes(struct irq_data *d)
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spin_lock_irqsave(&gic_lock, flags);
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for (i = 0; i < gic_vpes; i++) {
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gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR),
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mips_cm_vp_id(i));
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write_gic_vl_other(mips_cm_vp_id(i));
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write_gic_vo_smask(BIT(intr));
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}
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spin_unlock_irqrestore(&gic_lock, flags);
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@ -427,8 +388,7 @@ static void __init gic_basic_init(void)
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for (i = 0; i < gic_vpes; i++) {
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unsigned int j;
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gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR),
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mips_cm_vp_id(i));
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write_gic_vl_other(mips_cm_vp_id(i));
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for (j = 0; j < GIC_NUM_LOCAL_INTRS; j++) {
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if (!gic_local_irq_is_routable(j))
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continue;
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@ -712,10 +672,8 @@ static void __init __gic_init(unsigned long gic_base_addr,
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if (cpu_has_veic) {
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/* Set EIC mode for all VPEs */
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for_each_present_cpu(cpu) {
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gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR),
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mips_cm_vp_id(cpu));
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gic_write(GIC_REG(VPE_OTHER, GIC_VPE_CTL),
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GIC_VPE_CTL_EIC_MODE_MSK);
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write_gic_vl_other(mips_cm_vp_id(cpu));
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write_gic_vo_ctl(GIC_VX_CTL_EIC);
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}
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/* Always use vector 1 in EIC mode */
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@ -740,9 +698,7 @@ static void __init __gic_init(unsigned long gic_base_addr,
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*/
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if (IS_ENABLED(CONFIG_MIPS_CMP) &&
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gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) {
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timer_cpu_pin = gic_read32(GIC_REG(VPE_LOCAL,
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GIC_VPE_TIMER_MAP)) &
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GIC_MAP_MSK;
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timer_cpu_pin = read_gic_vl_timer_map() & GIC_MAP_PIN_MAP;
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irq_set_chained_handler(MIPS_CPU_IRQ_BASE +
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GIC_CPU_PIN_OFFSET +
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timer_cpu_pin,
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@ -13,58 +13,14 @@
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#define GIC_MAX_INTRS 256
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#define MSK(n) ((1 << (n)) - 1)
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/* Accessors */
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#define GIC_REG(segment, offset) (segment##_##SECTION_OFS + offset##_##OFS)
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/* GIC Address Space */
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#define VPE_LOCAL_SECTION_OFS 0x8000
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#define VPE_LOCAL_SECTION_SIZE 0x4000
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#define VPE_OTHER_SECTION_OFS 0xc000
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#define VPE_OTHER_SECTION_SIZE 0x4000
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#define USM_VISIBLE_SECTION_OFS 0x10000
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#define USM_VISIBLE_SECTION_SIZE 0x10000
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/* Register Map for Local Section */
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#define GIC_VPE_CTL_OFS 0x0000
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#define GIC_VPE_TIMER_MAP_OFS 0x0048
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#define GIC_VPE_OTHER_ADDR_OFS 0x0080
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#define GIC_VPE_WD_CONFIG0_OFS 0x0090
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#define GIC_VPE_WD_COUNT0_OFS 0x0094
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#define GIC_VPE_WD_INITIAL0_OFS 0x0098
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#define GIC_VPE_EIC_SHADOW_SET_BASE_OFS 0x0100
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#define GIC_VPE_EIC_SS(intr) (4 * (intr))
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#define GIC_VPE_EIC_VEC_BASE_OFS 0x0800
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#define GIC_VPE_EIC_VEC(intr) (4 * (intr))
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#define GIC_VPE_TENABLE_NMI_OFS 0x1000
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#define GIC_VPE_TENABLE_YQ_OFS 0x1004
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#define GIC_VPE_TENABLE_INT_31_0_OFS 0x1080
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#define GIC_VPE_TENABLE_INT_63_32_OFS 0x1084
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/* User Mode Visible Section Register Map */
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#define GIC_UMV_SH_COUNTER_31_00_OFS 0x0000
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#define GIC_UMV_SH_COUNTER_63_32_OFS 0x0004
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/* Masks */
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#define GIC_MAP_SHF 0
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#define GIC_MAP_MSK (MSK(6) << GIC_MAP_SHF)
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/* GIC_VPE_CTL Masks */
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#define GIC_VPE_CTL_FDC_RTBL_SHF 4
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#define GIC_VPE_CTL_FDC_RTBL_MSK (MSK(1) << GIC_VPE_CTL_FDC_RTBL_SHF)
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#define GIC_VPE_CTL_SWINT_RTBL_SHF 3
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#define GIC_VPE_CTL_SWINT_RTBL_MSK (MSK(1) << GIC_VPE_CTL_SWINT_RTBL_SHF)
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#define GIC_VPE_CTL_PERFCNT_RTBL_SHF 2
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#define GIC_VPE_CTL_PERFCNT_RTBL_MSK (MSK(1) << GIC_VPE_CTL_PERFCNT_RTBL_SHF)
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#define GIC_VPE_CTL_TIMER_RTBL_SHF 1
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#define GIC_VPE_CTL_TIMER_RTBL_MSK (MSK(1) << GIC_VPE_CTL_TIMER_RTBL_SHF)
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#define GIC_VPE_CTL_EIC_MODE_SHF 0
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#define GIC_VPE_CTL_EIC_MODE_MSK (MSK(1) << GIC_VPE_CTL_EIC_MODE_SHF)
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/* GIC nomenclature for Core Interrupt Pins. */
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#define GIC_CPU_INT0 0 /* Core Interrupt 2 */
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#define GIC_CPU_INT1 1 /* . */
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