renegade-project/linux-next
2
0
Fork 0
mirror of https://github.com/edk2-porting/linux-next.git synced 2024-12-17 17:53:56 +08:00
Code

[PATCH] atyfb: VT/GT cleanup

Browse Source 
Clean up VT and GT chip descriptions.

All B revision VT chips are called 264VT3. Verified from pictures of the
chips as the specs are a bit unlear in this.

GT revision B1 is Rage II, B2 is Rage II+. Specs and chip pictures seem
to agree.

VT revision A4 is 264VT2. Revision A3 is probably a plain 264VT.

Signed-off-by: Ville Syrjälä <syrjala@sci.fi>
Signed-off-by: Antonino Daplas <adaplas@pol.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Ville Syrjl 2006-01-09 20:53:31 -08:00 committed by Linus Torvalds
parent 69b569f5c0
commit 0c23b67c49
1 changed files with 44 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

68
drivers/video/aty/atyfb_base.c
View File

@ -380,11 +380,12 @@ static struct {
#ifdef CONFIG_FB_ATY_CT #ifdef CONFIG_FB_ATY_CT
{ PCI_CHIP_MACH64CT, "ATI264CT (Mach64 CT)", 135, 60, 60, 0, ATI_CHIP_264CT }, { PCI_CHIP_MACH64CT, "ATI264CT (Mach64 CT)", 135, 60, 60, 0, ATI_CHIP_264CT },
{ PCI_CHIP_MACH64ET, "ATI264ET (Mach64 ET)", 135, 60, 60, 0, ATI_CHIP_264ET }, { PCI_CHIP_MACH64ET, "ATI264ET (Mach64 ET)", 135, 60, 60, 0, ATI_CHIP_264ET },
{ PCI_CHIP_MACH64VT, "ATI264VT? (Mach64 VT)", 170, 67, 67, 80, ATI_CHIP_264VT },
{ PCI_CHIP_MACH64VT, "ATI264VT (Mach64 VT)", 170, 67, 67, 80, ATI_CHIP_264VT },
{ PCI_CHIP_MACH64GT, "3D RAGE (Mach64 GT)", 135, 63, 63, 80, ATI_CHIP_264GT }, { PCI_CHIP_MACH64GT, "3D RAGE (Mach64 GT)", 135, 63, 63, 80, ATI_CHIP_264GT },
/* FIXME { ...ATI_264GU, maybe ATI_CHIP_264GTDVD }, */
{ PCI_CHIP_MACH64GU, "3D RAGE II+ (Mach64 GTB)", 200, 67, 67, 100, ATI_CHIP_264GTB }, { PCI_CHIP_MACH64VU, "ATI264VT3 (Mach64 VU)", 200, 67, 67, 80, ATI_CHIP_264VT3 },
{ PCI_CHIP_MACH64VU, "ATI264VTB (Mach64 VU)", 200, 67, 67, 80, ATI_CHIP_264VT3 }, { PCI_CHIP_MACH64GU, "3D RAGE II+ (Mach64 GU)", 200, 67, 67, 100, ATI_CHIP_264GTB },
{ PCI_CHIP_MACH64LT, "3D RAGE LT (Mach64 LT)", 135, 63, 63, 0, ATI_CHIP_264LT }, { PCI_CHIP_MACH64LT, "3D RAGE LT (Mach64 LT)", 135, 63, 63, 0, ATI_CHIP_264LT },
/* FIXME chipset maybe ATI_CHIP_264LTPRO ? */ /* FIXME chipset maybe ATI_CHIP_264LTPRO ? */
@ -460,44 +461,63 @@ static int __devinit correct_chipset(struct atyfb_par *par)
#endif #endif
#ifdef CONFIG_FB_ATY_CT #ifdef CONFIG_FB_ATY_CT
case PCI_CHIP_MACH64VT: case PCI_CHIP_MACH64VT:
rev &= 0xc7; switch (rev & 0x07) {
if(rev == 0x00) { case 0x00:
name = "ATI264VTA3 (Mach64 VT)"; switch (rev & 0xc0) {
par->pll_limits.pll_max = 170; case 0x00:
par->pll_limits.mclk = 67; name = "ATI264VT (A3) (Mach64 VT)";
par->pll_limits.xclk = 67; par->pll_limits.pll_max = 170;
par->pll_limits.ecp_max = 80; par->pll_limits.mclk = 67;
par->features = ATI_CHIP_264VT; par->pll_limits.xclk = 67;
} else if(rev == 0x40) { par->pll_limits.ecp_max = 80;
name = "ATI264VTA4 (Mach64 VT)"; par->features = ATI_CHIP_264VT;
par->pll_limits.pll_max = 200; break;
par->pll_limits.mclk = 67; case 0x40:
par->pll_limits.xclk = 67; name = "ATI264VT2 (A4) (Mach64 VT)";
par->pll_limits.ecp_max = 80; par->pll_limits.pll_max = 200;
par->features = ATI_CHIP_264VT | M64F_MAGIC_POSTDIV; par->pll_limits.mclk = 67;
} else { par->pll_limits.xclk = 67;
name = "ATI264VTB (Mach64 VT)"; par->pll_limits.ecp_max = 80;
par->features = ATI_CHIP_264VT | M64F_MAGIC_POSTDIV;
break;
}
break;
case 0x01:
name = "ATI264VT3 (B1) (Mach64 VT)";
par->pll_limits.pll_max = 200; par->pll_limits.pll_max = 200;
par->pll_limits.mclk = 67; par->pll_limits.mclk = 67;
par->pll_limits.xclk = 67; par->pll_limits.xclk = 67;
par->pll_limits.ecp_max = 80; par->pll_limits.ecp_max = 80;
par->features = ATI_CHIP_264VTB; par->features = ATI_CHIP_264VTB;
break;
case 0x02:
name = "ATI264VT3 (B2) (Mach64 VT)";
par->pll_limits.pll_max = 200;
par->pll_limits.mclk = 67;
par->pll_limits.xclk = 67;
par->pll_limits.ecp_max = 80;
par->features = ATI_CHIP_264VT3;
break;
} }
break; break;
case PCI_CHIP_MACH64GT: case PCI_CHIP_MACH64GT:
rev &= 0x07; switch (rev & 0x07) {
if(rev == 0x01) { case 0x01:
name = "3D RAGE II (Mach64 GT)";
par->pll_limits.pll_max = 170; par->pll_limits.pll_max = 170;
par->pll_limits.mclk = 67; par->pll_limits.mclk = 67;
par->pll_limits.xclk = 67; par->pll_limits.xclk = 67;
par->pll_limits.ecp_max = 80; par->pll_limits.ecp_max = 80;
par->features = ATI_CHIP_264GTB; par->features = ATI_CHIP_264GTB;
} else if(rev == 0x02) { break;
case 0x02:
name = "3D RAGE II+ (Mach64 GT)";
par->pll_limits.pll_max = 200; par->pll_limits.pll_max = 200;
par->pll_limits.mclk = 67; par->pll_limits.mclk = 67;
par->pll_limits.xclk = 67; par->pll_limits.xclk = 67;
par->pll_limits.ecp_max = 100; par->pll_limits.ecp_max = 100;
par->features = ATI_CHIP_264GTB; par->features = ATI_CHIP_264GTB;
break;
} }
break; break;
#endif #endif