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clk: sunxi-ng: h3: Fix audio clock divider offset

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The code had a typo and got the wrong offset for the hardcoded divider, fix
that.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reported-by: Jean-Francois Moine <moinejf@free.fr>
Reported-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160711203448.18062-1-maxime.ripard@free-electrons.com
This commit is contained in:
Maxime Ripard 2016-07-11 22:34:47 +02:00 committed by Michael Turquette
parent 0577e4853b
commit 0bd8fa2608
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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@ -817,8 +817,8 @@ static void __init sun8i_h3_ccu_setup(struct device_node *node)
/* Force the PLL-Audio-1x divider to 4 */
val = readl(reg + SUN8I_H3_PLL_AUDIO_REG);
val &= ~GENMASK(4, 0);
writel(val | 3, reg + SUN8I_H3_PLL_AUDIO_REG);
val &= ~GENMASK(19, 16);
writel(val | (3 << 16), reg + SUN8I_H3_PLL_AUDIO_REG);
sunxi_ccu_probe(node, reg, &sun8i_h3_ccu_desc);
}