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clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics
This SoC has the 5th divisor for the mck0 master clock. Adapt the characteristics accordingly. Reported-by: Mihai Sain <mihai.sain@microchip.com> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1605800597-16720-6-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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@ -775,13 +775,13 @@ static const struct clk_pll_characteristics pll_characteristics = {
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/* MCK0 characteristics. */
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/* MCK0 characteristics. */
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static const struct clk_master_characteristics mck0_characteristics = {
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static const struct clk_master_characteristics mck0_characteristics = {
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.output = { .min = 140000000, .max = 200000000 },
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.output = { .min = 140000000, .max = 200000000 },
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.divisors = { 1, 2, 4, 3 },
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.divisors = { 1, 2, 4, 3, 5 },
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.have_div3_pres = 1,
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.have_div3_pres = 1,
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};
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};
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/* MCK0 layout. */
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/* MCK0 layout. */
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static const struct clk_master_layout mck0_layout = {
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static const struct clk_master_layout mck0_layout = {
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.mask = 0x373,
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.mask = 0x773,
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.pres_shift = 4,
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.pres_shift = 4,
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.offset = 0x28,
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.offset = 0x28,
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};
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};
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