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https://github.com/edk2-porting/linux-next.git
synced 2024-12-24 13:13:57 +08:00
[SPARC64]: Kill pci_controller->resource_adjust()
All the implementations can be identical and generic, so no need for controller specific methods. Signed-off-by: David S. Miller <davem@davemloft.net>
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parent
3487a1f9e7
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0bae5f81b6
@ -469,6 +469,13 @@ static void __init apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p)
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*last_p = last;
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}
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static void __init pci_resource_adjust(struct resource *res,
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struct resource *root)
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{
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res->start += root->start;
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res->end += root->start;
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}
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/* Cook up fake bus resources for SUNW,simba PCI bridges which lack
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* a proper 'ranges' property.
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*/
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@ -486,7 +493,7 @@ static void __init apb_fake_ranges(struct pci_dev *dev,
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res->start = (first << 21);
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res->end = (last << 21) + ((1 << 21) - 1);
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res->flags = IORESOURCE_IO;
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pbm->parent->resource_adjust(dev, res, &pbm->io_space);
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pci_resource_adjust(res, &pbm->io_space);
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pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map);
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apb_calc_first_last(map, &first, &last);
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@ -494,7 +501,7 @@ static void __init apb_fake_ranges(struct pci_dev *dev,
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res->start = (first << 21);
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res->end = (last << 21) + ((1 << 21) - 1);
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res->flags = IORESOURCE_MEM;
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pbm->parent->resource_adjust(dev, res, &pbm->mem_space);
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pci_resource_adjust(res, &pbm->mem_space);
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}
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static void __init pci_of_scan_bus(struct pci_pbm_info *pbm,
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@ -594,7 +601,7 @@ void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm,
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* layer routine that can calculate a resource for a given
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* range property value in a PCI device.
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*/
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pbm->parent->resource_adjust(dev, res, root);
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pci_resource_adjust(res, root);
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}
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simba_cont:
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sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
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@ -803,7 +810,7 @@ void pcibios_resource_to_bus(struct pci_dev *pdev, struct pci_bus_region *region
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else
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root = &pbm->mem_space;
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pbm->parent->resource_adjust(pdev, &zero_res, root);
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pci_resource_adjust(&zero_res, root);
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region->start = res->start - zero_res.start;
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region->end = res->end - zero_res.start;
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@ -824,7 +831,7 @@ void pcibios_bus_to_resource(struct pci_dev *pdev, struct resource *res,
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else
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root = &pbm->mem_space;
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pbm->parent->resource_adjust(pdev, res, root);
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pci_resource_adjust(res, root);
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}
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EXPORT_SYMBOL(pcibios_bus_to_resource);
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@ -894,14 +894,6 @@ static void psycho_register_error_handlers(struct pci_controller_info *p)
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}
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/* PSYCHO boot time probing and initialization. */
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static void psycho_resource_adjust(struct pci_dev *pdev,
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struct resource *res,
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struct resource *root)
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{
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res->start += root->start;
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res->end += root->start;
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}
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static void psycho_base_address_update(struct pci_dev *pdev, int resource)
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{
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struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
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@ -1218,7 +1210,6 @@ void psycho_init(struct device_node *dp, char *model_name)
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p->pbms_same_domain = 0;
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p->scan_bus = psycho_scan_bus;
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p->base_address_update = psycho_base_address_update;
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p->resource_adjust = psycho_resource_adjust;
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p->pci_ops = &psycho_ops;
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prop = of_find_property(dp, "reg", NULL);
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@ -862,22 +862,6 @@ static void sabre_register_error_handlers(struct pci_controller_info *p)
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sabre_write(base + SABRE_PCICTRL, tmp);
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}
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static void sabre_resource_adjust(struct pci_dev *pdev,
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struct resource *res,
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struct resource *root)
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{
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struct pci_pbm_info *pbm = pdev->bus->sysdata;
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unsigned long base;
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if (res->flags & IORESOURCE_IO)
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base = pbm->controller_regs + SABRE_IOSPACE;
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else
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base = pbm->controller_regs + SABRE_MEMSPACE;
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res->start += base;
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res->end += base;
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}
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static void sabre_base_address_update(struct pci_dev *pdev, int resource)
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{
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struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
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@ -1116,7 +1100,6 @@ void sabre_init(struct device_node *dp, char *model_name)
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p->pbms_same_domain = 1;
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p->scan_bus = sabre_scan_bus;
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p->base_address_update = sabre_base_address_update;
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p->resource_adjust = sabre_resource_adjust;
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p->pci_ops = &sabre_ops;
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/*
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@ -1295,14 +1295,6 @@ static void schizo_base_address_update(struct pci_dev *pdev, int resource)
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pci_write_config_dword(pdev, where + 4, 0);
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}
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static void schizo_resource_adjust(struct pci_dev *pdev,
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struct resource *res,
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struct resource *root)
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{
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res->start += root->start;
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res->end += root->start;
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}
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#define SCHIZO_STRBUF_CONTROL (0x02800UL)
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#define SCHIZO_STRBUF_FLUSH (0x02808UL)
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#define SCHIZO_STRBUF_FSYNC (0x02810UL)
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@ -1670,7 +1662,6 @@ static void __schizo_init(struct device_node *dp, char *model_name, int chip_typ
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p->index = pci_num_controllers++;
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p->scan_bus = schizo_scan_bus;
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p->base_address_update = schizo_base_address_update;
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p->resource_adjust = schizo_resource_adjust;
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p->pci_ops = &schizo_ops;
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/* Like PSYCHO we have a 2GB aligned area for memory space. */
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@ -743,14 +743,6 @@ static void pci_sun4v_base_address_update(struct pci_dev *pdev, int resource)
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pci_write_config_dword(pdev, where + 4, 0);
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}
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static void pci_sun4v_resource_adjust(struct pci_dev *pdev,
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struct resource *res,
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struct resource *root)
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{
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res->start += root->start;
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res->end += root->start;
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}
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static unsigned long probe_existing_entries(struct pci_pbm_info *pbm,
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struct pci_iommu *iommu)
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{
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@ -1387,7 +1379,6 @@ void sun4v_pci_init(struct device_node *dp, char *model_name)
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p->scan_bus = pci_sun4v_scan_bus;
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p->base_address_update = pci_sun4v_base_address_update;
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p->resource_adjust = pci_sun4v_resource_adjust;
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#ifdef CONFIG_PCI_MSI
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p->setup_msi_irq = pci_sun4v_setup_msi_irq;
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p->teardown_msi_irq = pci_sun4v_teardown_msi_irq;
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@ -225,7 +225,6 @@ struct pci_controller_info {
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/* Operations which are controller specific. */
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void (*scan_bus)(struct pci_controller_info *);
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void (*base_address_update)(struct pci_dev *, int);
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void (*resource_adjust)(struct pci_dev *, struct resource *, struct resource *);
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#ifdef CONFIG_PCI_MSI
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int (*setup_msi_irq)(unsigned int *virt_irq_p, struct pci_dev *pdev,
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