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rtc: Add driver for Microchip PolarFire SoC
Add support for the built-in RTC on Microchip PolarFire SoC Co-Developed-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20220601123320.2861043-2-conor.dooley@microchip.com
This commit is contained in:
Conor Dooley
Alexandre Belloni
parent
3f4a332247
commit
0b31d70359
@ -1973,4 +1973,14 @@ config RTC_DRV_MSC313
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This driver can also be built as a module, if so, the module
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will be called "rtc-msc313".
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config RTC_DRV_POLARFIRE_SOC
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tristate "Microchip PolarFire SoC built-in RTC"
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depends on SOC_MICROCHIP_POLARFIRE
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help
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If you say yes here you will get support for the
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built-in RTC on Polarfire SoC.
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This driver can also be built as a module, if so, the module
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will be called "rtc-mpfs".
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endif # RTC_CLASS
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@ -130,6 +130,7 @@ obj-$(CONFIG_RTC_DRV_PIC32) += rtc-pic32.o
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obj-$(CONFIG_RTC_DRV_PL030) += rtc-pl030.o
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obj-$(CONFIG_RTC_DRV_PL031) += rtc-pl031.o
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obj-$(CONFIG_RTC_DRV_PM8XXX) += rtc-pm8xxx.o
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obj-$(CONFIG_RTC_DRV_POLARFIRE_SOC) += rtc-mpfs.o
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obj-$(CONFIG_RTC_DRV_PS3) += rtc-ps3.o
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obj-$(CONFIG_RTC_DRV_PXA) += rtc-pxa.o
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obj-$(CONFIG_RTC_DRV_R7301) += rtc-r7301.o
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326
drivers/rtc/rtc-mpfs.c
Normal file
326
drivers/rtc/rtc-mpfs.c
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@ -0,0 +1,326 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Microchip MPFS RTC driver
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*
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* Copyright (c) 2021-2022 Microchip Corporation. All rights reserved.
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*
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* Author: Daire McNamara <daire.mcnamara@microchip.com>
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* & Conor Dooley <conor.dooley@microchip.com>
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*/
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#include "linux/bits.h"
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#include "linux/iopoll.h"
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_wakeirq.h>
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#include <linux/slab.h>
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#include <linux/rtc.h>
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#define CONTROL_REG 0x00
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#define MODE_REG 0x04
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#define PRESCALER_REG 0x08
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#define ALARM_LOWER_REG 0x0c
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#define ALARM_UPPER_REG 0x10
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#define COMPARE_LOWER_REG 0x14
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#define COMPARE_UPPER_REG 0x18
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#define DATETIME_LOWER_REG 0x20
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#define DATETIME_UPPER_REG 0x24
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#define CONTROL_RUNNING_BIT BIT(0)
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#define CONTROL_START_BIT BIT(0)
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#define CONTROL_STOP_BIT BIT(1)
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#define CONTROL_ALARM_ON_BIT BIT(2)
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#define CONTROL_ALARM_OFF_BIT BIT(3)
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#define CONTROL_RESET_BIT BIT(4)
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#define CONTROL_UPLOAD_BIT BIT(5)
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#define CONTROL_DOWNLOAD_BIT BIT(6)
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#define CONTROL_MATCH_BIT BIT(7)
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#define CONTROL_WAKEUP_CLR_BIT BIT(8)
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#define CONTROL_WAKEUP_SET_BIT BIT(9)
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#define CONTROL_UPDATED_BIT BIT(10)
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#define MODE_CLOCK_CALENDAR BIT(0)
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#define MODE_WAKE_EN BIT(1)
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#define MODE_WAKE_RESET BIT(2)
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#define MODE_WAKE_CONTINUE BIT(3)
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#define MAX_PRESCALER_COUNT GENMASK(25, 0)
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#define DATETIME_UPPER_MASK GENMASK(29, 0)
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#define ALARM_UPPER_MASK GENMASK(10, 0)
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#define UPLOAD_TIMEOUT_US 50
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struct mpfs_rtc_dev {
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struct rtc_device *rtc;
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void __iomem *base;
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};
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static void mpfs_rtc_start(struct mpfs_rtc_dev *rtcdev)
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{
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u32 ctrl;
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ctrl = readl(rtcdev->base + CONTROL_REG);
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ctrl &= ~CONTROL_STOP_BIT;
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ctrl |= CONTROL_START_BIT;
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writel(ctrl, rtcdev->base + CONTROL_REG);
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}
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static void mpfs_rtc_clear_irq(struct mpfs_rtc_dev *rtcdev)
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{
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u32 val = readl(rtcdev->base + CONTROL_REG);
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val &= ~(CONTROL_ALARM_ON_BIT | CONTROL_STOP_BIT);
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val |= CONTROL_ALARM_OFF_BIT;
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writel(val, rtcdev->base + CONTROL_REG);
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/*
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* Ensure that the posted write to the CONTROL_REG register completed before
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* returning from this function. Not doing this may result in the interrupt
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* only being cleared some time after this function returns.
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*/
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(void)readl(rtcdev->base + CONTROL_REG);
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}
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static int mpfs_rtc_readtime(struct device *dev, struct rtc_time *tm)
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{
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struct mpfs_rtc_dev *rtcdev = dev_get_drvdata(dev);
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u64 time;
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time = readl(rtcdev->base + DATETIME_LOWER_REG);
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time |= ((u64)readl(rtcdev->base + DATETIME_UPPER_REG) & DATETIME_UPPER_MASK) << 32;
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rtc_time64_to_tm(time, tm);
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return 0;
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}
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static int mpfs_rtc_settime(struct device *dev, struct rtc_time *tm)
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{
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struct mpfs_rtc_dev *rtcdev = dev_get_drvdata(dev);
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u32 ctrl, prog;
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u64 time;
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int ret;
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time = rtc_tm_to_time64(tm);
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writel((u32)time, rtcdev->base + DATETIME_LOWER_REG);
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writel((u32)(time >> 32) & DATETIME_UPPER_MASK, rtcdev->base + DATETIME_UPPER_REG);
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ctrl = readl(rtcdev->base + CONTROL_REG);
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ctrl &= ~CONTROL_STOP_BIT;
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ctrl |= CONTROL_UPLOAD_BIT;
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writel(ctrl, rtcdev->base + CONTROL_REG);
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ret = read_poll_timeout(readl, prog, prog & CONTROL_UPLOAD_BIT, 0, UPLOAD_TIMEOUT_US,
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false, rtcdev->base + CONTROL_REG);
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if (ret) {
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dev_err(dev, "timed out uploading time to rtc");
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return ret;
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}
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mpfs_rtc_start(rtcdev);
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return 0;
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}
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static int mpfs_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
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{
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struct mpfs_rtc_dev *rtcdev = dev_get_drvdata(dev);
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u32 mode = readl(rtcdev->base + MODE_REG);
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u64 time;
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alrm->enabled = mode & MODE_WAKE_EN;
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time = (u64)readl(rtcdev->base + ALARM_LOWER_REG) << 32;
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time |= (readl(rtcdev->base + ALARM_UPPER_REG) & ALARM_UPPER_MASK);
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rtc_time64_to_tm(time, &alrm->time);
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return 0;
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}
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static int mpfs_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
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{
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struct mpfs_rtc_dev *rtcdev = dev_get_drvdata(dev);
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u32 mode, ctrl;
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u64 time;
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/* Disable the alarm before updating */
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ctrl = readl(rtcdev->base + CONTROL_REG);
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ctrl |= CONTROL_ALARM_OFF_BIT;
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writel(ctrl, rtcdev->base + CONTROL_REG);
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time = rtc_tm_to_time64(&alrm->time);
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writel((u32)time, rtcdev->base + ALARM_LOWER_REG);
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writel((u32)(time >> 32) & ALARM_UPPER_MASK, rtcdev->base + ALARM_UPPER_REG);
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/* Bypass compare register in alarm mode */
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writel(GENMASK(31, 0), rtcdev->base + COMPARE_LOWER_REG);
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writel(GENMASK(29, 0), rtcdev->base + COMPARE_UPPER_REG);
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/* Configure the RTC to enable the alarm. */
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ctrl = readl(rtcdev->base + CONTROL_REG);
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mode = readl(rtcdev->base + MODE_REG);
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if (alrm->enabled) {
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mode = MODE_WAKE_EN | MODE_WAKE_CONTINUE;
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/* Enable the alarm */
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ctrl &= ~CONTROL_ALARM_OFF_BIT;
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ctrl |= CONTROL_ALARM_ON_BIT;
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}
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ctrl &= ~CONTROL_STOP_BIT;
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ctrl |= CONTROL_START_BIT;
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writel(ctrl, rtcdev->base + CONTROL_REG);
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writel(mode, rtcdev->base + MODE_REG);
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return 0;
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}
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static int mpfs_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
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{
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struct mpfs_rtc_dev *rtcdev = dev_get_drvdata(dev);
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u32 ctrl;
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ctrl = readl(rtcdev->base + CONTROL_REG);
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ctrl &= ~(CONTROL_ALARM_ON_BIT | CONTROL_ALARM_OFF_BIT | CONTROL_STOP_BIT);
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if (enabled)
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ctrl |= CONTROL_ALARM_ON_BIT;
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else
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ctrl |= CONTROL_ALARM_OFF_BIT;
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writel(ctrl, rtcdev->base + CONTROL_REG);
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return 0;
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}
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static inline struct clk *mpfs_rtc_init_clk(struct device *dev)
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{
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struct clk *clk;
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int ret;
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clk = devm_clk_get(dev, "rtc");
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if (IS_ERR(clk))
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return clk;
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ret = clk_prepare_enable(clk);
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if (ret)
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return ERR_PTR(ret);
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devm_add_action_or_reset(dev, (void (*) (void *))clk_disable_unprepare, clk);
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return clk;
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}
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static irqreturn_t mpfs_rtc_wakeup_irq_handler(int irq, void *dev)
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{
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struct mpfs_rtc_dev *rtcdev = dev;
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unsigned long pending;
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pending = readl(rtcdev->base + CONTROL_REG);
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pending &= CONTROL_ALARM_ON_BIT;
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mpfs_rtc_clear_irq(rtcdev);
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rtc_update_irq(rtcdev->rtc, 1, RTC_IRQF | RTC_AF);
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return IRQ_HANDLED;
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}
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static const struct rtc_class_ops mpfs_rtc_ops = {
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.read_time = mpfs_rtc_readtime,
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.set_time = mpfs_rtc_settime,
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.read_alarm = mpfs_rtc_readalarm,
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.set_alarm = mpfs_rtc_setalarm,
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.alarm_irq_enable = mpfs_rtc_alarm_irq_enable,
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};
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static int mpfs_rtc_probe(struct platform_device *pdev)
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{
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struct mpfs_rtc_dev *rtcdev;
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struct clk *clk;
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u32 prescaler;
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int wakeup_irq, ret;
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rtcdev = devm_kzalloc(&pdev->dev, sizeof(struct mpfs_rtc_dev), GFP_KERNEL);
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if (!rtcdev)
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return -ENOMEM;
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platform_set_drvdata(pdev, rtcdev);
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rtcdev->rtc = devm_rtc_allocate_device(&pdev->dev);
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if (IS_ERR(rtcdev->rtc))
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return PTR_ERR(rtcdev->rtc);
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rtcdev->rtc->ops = &mpfs_rtc_ops;
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/* range is capped by alarm max, lower reg is 31:0 & upper is 10:0 */
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rtcdev->rtc->range_max = GENMASK_ULL(42, 0);
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clk = mpfs_rtc_init_clk(&pdev->dev);
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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rtcdev->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(rtcdev->base)) {
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dev_dbg(&pdev->dev, "invalid ioremap resources\n");
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return PTR_ERR(rtcdev->base);
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}
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wakeup_irq = platform_get_irq(pdev, 0);
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if (wakeup_irq <= 0) {
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dev_dbg(&pdev->dev, "could not get wakeup irq\n");
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return wakeup_irq;
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}
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ret = devm_request_irq(&pdev->dev, wakeup_irq, mpfs_rtc_wakeup_irq_handler, 0,
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dev_name(&pdev->dev), rtcdev);
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if (ret) {
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dev_dbg(&pdev->dev, "could not request wakeup irq\n");
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return ret;
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}
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/* prescaler hardware adds 1 to reg value */
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prescaler = clk_get_rate(devm_clk_get(&pdev->dev, "rtcref")) - 1;
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if (prescaler > MAX_PRESCALER_COUNT) {
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dev_dbg(&pdev->dev, "invalid prescaler %d\n", prescaler);
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return -EINVAL;
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}
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writel(prescaler, rtcdev->base + PRESCALER_REG);
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dev_info(&pdev->dev, "prescaler set to: 0x%X \r\n", prescaler);
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device_init_wakeup(&pdev->dev, true);
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ret = dev_pm_set_wake_irq(&pdev->dev, wakeup_irq);
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if (ret)
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dev_err(&pdev->dev, "failed to enable irq wake\n");
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return devm_rtc_register_device(rtcdev->rtc);
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}
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static int mpfs_rtc_remove(struct platform_device *pdev)
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{
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dev_pm_clear_wake_irq(&pdev->dev);
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return 0;
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}
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static const struct of_device_id mpfs_rtc_of_match[] = {
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{ .compatible = "microchip,mpfs-rtc" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, mpfs_rtc_of_match);
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static struct platform_driver mpfs_rtc_driver = {
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.probe = mpfs_rtc_probe,
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.remove = mpfs_rtc_remove,
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.driver = {
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.name = "mpfs_rtc",
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.of_match_table = mpfs_rtc_of_match,
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},
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};
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module_platform_driver(mpfs_rtc_driver);
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MODULE_DESCRIPTION("Real time clock for Microchip Polarfire SoC");
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MODULE_AUTHOR("Daire McNamara <daire.mcnamara@microchip.com>");
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MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
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MODULE_LICENSE("GPL");
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