mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-19 10:44:14 +08:00
x86, dmar: move page fault handling code to dmar.c
Impact: code movement Move page fault handling code to dmar.c This will be shared both by DMA-remapping and Intr-remapping code. Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
This commit is contained in:
Suresh Siddha
H. Peter Anvin
parent
4c5502b1c5
commit
0ac2491f57
@ -31,6 +31,8 @@
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#include <linux/iova.h>
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#include <linux/intel-iommu.h>
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#include <linux/timer.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#undef PREFIX
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#define PREFIX "DMAR:"
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@ -812,3 +814,192 @@ int dmar_enable_qi(struct intel_iommu *iommu)
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return 0;
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}
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/* iommu interrupt handling. Most stuff are MSI-like. */
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static const char *fault_reason_strings[] =
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{
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"Software",
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"Present bit in root entry is clear",
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"Present bit in context entry is clear",
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"Invalid context entry",
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"Access beyond MGAW",
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"PTE Write access is not set",
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"PTE Read access is not set",
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"Next page table ptr is invalid",
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"Root table address invalid",
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"Context table ptr is invalid",
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"non-zero reserved fields in RTP",
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"non-zero reserved fields in CTP",
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"non-zero reserved fields in PTE",
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};
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#define MAX_FAULT_REASON_IDX (ARRAY_SIZE(fault_reason_strings) - 1)
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const char *dmar_get_fault_reason(u8 fault_reason)
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{
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if (fault_reason > MAX_FAULT_REASON_IDX)
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return "Unknown";
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else
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return fault_reason_strings[fault_reason];
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}
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void dmar_msi_unmask(unsigned int irq)
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{
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struct intel_iommu *iommu = get_irq_data(irq);
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unsigned long flag;
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/* unmask it */
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spin_lock_irqsave(&iommu->register_lock, flag);
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writel(0, iommu->reg + DMAR_FECTL_REG);
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/* Read a reg to force flush the post write */
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readl(iommu->reg + DMAR_FECTL_REG);
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spin_unlock_irqrestore(&iommu->register_lock, flag);
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}
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void dmar_msi_mask(unsigned int irq)
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{
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unsigned long flag;
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struct intel_iommu *iommu = get_irq_data(irq);
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/* mask it */
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spin_lock_irqsave(&iommu->register_lock, flag);
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writel(DMA_FECTL_IM, iommu->reg + DMAR_FECTL_REG);
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/* Read a reg to force flush the post write */
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readl(iommu->reg + DMAR_FECTL_REG);
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spin_unlock_irqrestore(&iommu->register_lock, flag);
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}
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void dmar_msi_write(int irq, struct msi_msg *msg)
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{
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struct intel_iommu *iommu = get_irq_data(irq);
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unsigned long flag;
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spin_lock_irqsave(&iommu->register_lock, flag);
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writel(msg->data, iommu->reg + DMAR_FEDATA_REG);
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writel(msg->address_lo, iommu->reg + DMAR_FEADDR_REG);
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writel(msg->address_hi, iommu->reg + DMAR_FEUADDR_REG);
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spin_unlock_irqrestore(&iommu->register_lock, flag);
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}
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void dmar_msi_read(int irq, struct msi_msg *msg)
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{
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struct intel_iommu *iommu = get_irq_data(irq);
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unsigned long flag;
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spin_lock_irqsave(&iommu->register_lock, flag);
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msg->data = readl(iommu->reg + DMAR_FEDATA_REG);
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msg->address_lo = readl(iommu->reg + DMAR_FEADDR_REG);
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msg->address_hi = readl(iommu->reg + DMAR_FEUADDR_REG);
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spin_unlock_irqrestore(&iommu->register_lock, flag);
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}
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static int dmar_fault_do_one(struct intel_iommu *iommu, int type,
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u8 fault_reason, u16 source_id, unsigned long long addr)
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{
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const char *reason;
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reason = dmar_get_fault_reason(fault_reason);
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printk(KERN_ERR
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"DMAR:[%s] Request device [%02x:%02x.%d] "
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"fault addr %llx \n"
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"DMAR:[fault reason %02d] %s\n",
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(type ? "DMA Read" : "DMA Write"),
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(source_id >> 8), PCI_SLOT(source_id & 0xFF),
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PCI_FUNC(source_id & 0xFF), addr, fault_reason, reason);
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return 0;
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}
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#define PRIMARY_FAULT_REG_LEN (16)
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static irqreturn_t dmar_fault(int irq, void *dev_id)
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{
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struct intel_iommu *iommu = dev_id;
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int reg, fault_index;
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u32 fault_status;
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unsigned long flag;
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spin_lock_irqsave(&iommu->register_lock, flag);
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fault_status = readl(iommu->reg + DMAR_FSTS_REG);
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/* TBD: ignore advanced fault log currently */
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if (!(fault_status & DMA_FSTS_PPF))
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goto clear_overflow;
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fault_index = dma_fsts_fault_record_index(fault_status);
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reg = cap_fault_reg_offset(iommu->cap);
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while (1) {
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u8 fault_reason;
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u16 source_id;
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u64 guest_addr;
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int type;
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u32 data;
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/* highest 32 bits */
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data = readl(iommu->reg + reg +
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fault_index * PRIMARY_FAULT_REG_LEN + 12);
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if (!(data & DMA_FRCD_F))
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break;
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fault_reason = dma_frcd_fault_reason(data);
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type = dma_frcd_type(data);
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data = readl(iommu->reg + reg +
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fault_index * PRIMARY_FAULT_REG_LEN + 8);
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source_id = dma_frcd_source_id(data);
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guest_addr = dmar_readq(iommu->reg + reg +
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fault_index * PRIMARY_FAULT_REG_LEN);
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guest_addr = dma_frcd_page_addr(guest_addr);
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/* clear the fault */
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writel(DMA_FRCD_F, iommu->reg + reg +
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fault_index * PRIMARY_FAULT_REG_LEN + 12);
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spin_unlock_irqrestore(&iommu->register_lock, flag);
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dmar_fault_do_one(iommu, type, fault_reason,
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source_id, guest_addr);
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fault_index++;
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if (fault_index > cap_num_fault_regs(iommu->cap))
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fault_index = 0;
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spin_lock_irqsave(&iommu->register_lock, flag);
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}
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clear_overflow:
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/* clear primary fault overflow */
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fault_status = readl(iommu->reg + DMAR_FSTS_REG);
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if (fault_status & DMA_FSTS_PFO)
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writel(DMA_FSTS_PFO, iommu->reg + DMAR_FSTS_REG);
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spin_unlock_irqrestore(&iommu->register_lock, flag);
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return IRQ_HANDLED;
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}
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int dmar_set_interrupt(struct intel_iommu *iommu)
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{
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int irq, ret;
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irq = create_irq();
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if (!irq) {
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printk(KERN_ERR "IOMMU: no free vectors\n");
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return -EINVAL;
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}
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set_irq_data(irq, iommu);
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iommu->irq = irq;
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ret = arch_setup_dmar_msi(irq);
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if (ret) {
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set_irq_data(irq, NULL);
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iommu->irq = 0;
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destroy_irq(irq);
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return 0;
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}
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/* Force fault register is cleared */
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dmar_fault(irq, iommu);
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ret = request_irq(irq, dmar_fault, 0, iommu->name, iommu);
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if (ret)
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printk(KERN_ERR "IOMMU: can't request irq\n");
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return ret;
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}
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@ -1004,194 +1004,6 @@ static int iommu_disable_translation(struct intel_iommu *iommu)
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return 0;
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}
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/* iommu interrupt handling. Most stuff are MSI-like. */
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static const char *fault_reason_strings[] =
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{
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"Software",
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"Present bit in root entry is clear",
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"Present bit in context entry is clear",
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"Invalid context entry",
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"Access beyond MGAW",
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"PTE Write access is not set",
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"PTE Read access is not set",
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"Next page table ptr is invalid",
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"Root table address invalid",
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"Context table ptr is invalid",
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"non-zero reserved fields in RTP",
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"non-zero reserved fields in CTP",
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"non-zero reserved fields in PTE",
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};
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#define MAX_FAULT_REASON_IDX (ARRAY_SIZE(fault_reason_strings) - 1)
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const char *dmar_get_fault_reason(u8 fault_reason)
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{
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if (fault_reason > MAX_FAULT_REASON_IDX)
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return "Unknown";
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else
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return fault_reason_strings[fault_reason];
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}
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void dmar_msi_unmask(unsigned int irq)
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{
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struct intel_iommu *iommu = get_irq_data(irq);
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unsigned long flag;
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/* unmask it */
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spin_lock_irqsave(&iommu->register_lock, flag);
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writel(0, iommu->reg + DMAR_FECTL_REG);
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/* Read a reg to force flush the post write */
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readl(iommu->reg + DMAR_FECTL_REG);
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spin_unlock_irqrestore(&iommu->register_lock, flag);
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}
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void dmar_msi_mask(unsigned int irq)
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{
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unsigned long flag;
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struct intel_iommu *iommu = get_irq_data(irq);
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/* mask it */
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spin_lock_irqsave(&iommu->register_lock, flag);
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writel(DMA_FECTL_IM, iommu->reg + DMAR_FECTL_REG);
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/* Read a reg to force flush the post write */
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readl(iommu->reg + DMAR_FECTL_REG);
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spin_unlock_irqrestore(&iommu->register_lock, flag);
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}
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void dmar_msi_write(int irq, struct msi_msg *msg)
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{
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struct intel_iommu *iommu = get_irq_data(irq);
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unsigned long flag;
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spin_lock_irqsave(&iommu->register_lock, flag);
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writel(msg->data, iommu->reg + DMAR_FEDATA_REG);
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writel(msg->address_lo, iommu->reg + DMAR_FEADDR_REG);
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writel(msg->address_hi, iommu->reg + DMAR_FEUADDR_REG);
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spin_unlock_irqrestore(&iommu->register_lock, flag);
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}
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void dmar_msi_read(int irq, struct msi_msg *msg)
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{
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struct intel_iommu *iommu = get_irq_data(irq);
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unsigned long flag;
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spin_lock_irqsave(&iommu->register_lock, flag);
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msg->data = readl(iommu->reg + DMAR_FEDATA_REG);
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msg->address_lo = readl(iommu->reg + DMAR_FEADDR_REG);
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msg->address_hi = readl(iommu->reg + DMAR_FEUADDR_REG);
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spin_unlock_irqrestore(&iommu->register_lock, flag);
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}
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static int iommu_page_fault_do_one(struct intel_iommu *iommu, int type,
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u8 fault_reason, u16 source_id, unsigned long long addr)
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{
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const char *reason;
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reason = dmar_get_fault_reason(fault_reason);
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printk(KERN_ERR
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"DMAR:[%s] Request device [%02x:%02x.%d] "
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"fault addr %llx \n"
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"DMAR:[fault reason %02d] %s\n",
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(type ? "DMA Read" : "DMA Write"),
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(source_id >> 8), PCI_SLOT(source_id & 0xFF),
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PCI_FUNC(source_id & 0xFF), addr, fault_reason, reason);
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return 0;
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}
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#define PRIMARY_FAULT_REG_LEN (16)
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static irqreturn_t iommu_page_fault(int irq, void *dev_id)
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{
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struct intel_iommu *iommu = dev_id;
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int reg, fault_index;
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u32 fault_status;
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unsigned long flag;
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spin_lock_irqsave(&iommu->register_lock, flag);
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fault_status = readl(iommu->reg + DMAR_FSTS_REG);
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/* TBD: ignore advanced fault log currently */
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if (!(fault_status & DMA_FSTS_PPF))
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goto clear_overflow;
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fault_index = dma_fsts_fault_record_index(fault_status);
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reg = cap_fault_reg_offset(iommu->cap);
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while (1) {
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u8 fault_reason;
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u16 source_id;
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u64 guest_addr;
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int type;
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u32 data;
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/* highest 32 bits */
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data = readl(iommu->reg + reg +
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fault_index * PRIMARY_FAULT_REG_LEN + 12);
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if (!(data & DMA_FRCD_F))
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break;
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fault_reason = dma_frcd_fault_reason(data);
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type = dma_frcd_type(data);
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data = readl(iommu->reg + reg +
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fault_index * PRIMARY_FAULT_REG_LEN + 8);
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source_id = dma_frcd_source_id(data);
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guest_addr = dmar_readq(iommu->reg + reg +
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fault_index * PRIMARY_FAULT_REG_LEN);
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guest_addr = dma_frcd_page_addr(guest_addr);
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/* clear the fault */
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writel(DMA_FRCD_F, iommu->reg + reg +
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fault_index * PRIMARY_FAULT_REG_LEN + 12);
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spin_unlock_irqrestore(&iommu->register_lock, flag);
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iommu_page_fault_do_one(iommu, type, fault_reason,
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source_id, guest_addr);
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fault_index++;
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if (fault_index > cap_num_fault_regs(iommu->cap))
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fault_index = 0;
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spin_lock_irqsave(&iommu->register_lock, flag);
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}
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clear_overflow:
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/* clear primary fault overflow */
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fault_status = readl(iommu->reg + DMAR_FSTS_REG);
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if (fault_status & DMA_FSTS_PFO)
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writel(DMA_FSTS_PFO, iommu->reg + DMAR_FSTS_REG);
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spin_unlock_irqrestore(&iommu->register_lock, flag);
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return IRQ_HANDLED;
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}
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int dmar_set_interrupt(struct intel_iommu *iommu)
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{
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int irq, ret;
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irq = create_irq();
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if (!irq) {
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printk(KERN_ERR "IOMMU: no free vectors\n");
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return -EINVAL;
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}
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set_irq_data(irq, iommu);
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iommu->irq = irq;
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ret = arch_setup_dmar_msi(irq);
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if (ret) {
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set_irq_data(irq, NULL);
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iommu->irq = 0;
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destroy_irq(irq);
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return 0;
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}
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/* Force fault register is cleared */
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iommu_page_fault(irq, iommu);
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ret = request_irq(irq, iommu_page_fault, 0, iommu->name, iommu);
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if (ret)
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printk(KERN_ERR "IOMMU: can't request irq\n");
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return ret;
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}
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static int iommu_init_domains(struct intel_iommu *iommu)
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{
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