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drm/i915/kbl: Add WaDisableSbeCacheDispatchPortSharing

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This is needed for all kbl revision.

v2: Don't add revid checks to generic gen9 init (Arun)

References: HSD#2135593
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465309159-30531-21-git-send-email-mika.kuoppala@intel.com
(cherry picked from commit 954337aa96)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
This commit is contained in:
Mika Kuoppala 2016-06-07 17:19:12 +03:00 committed by Mika Kuoppala
parent 3af5f1137c
commit 0a3e3f047b
1 changed files with 5 additions and 0 deletions
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5
drivers/gpu/drm/i915/intel_ringbuffer.c
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@ -1233,6 +1233,11 @@ static int kbl_init_workarounds(struct intel_engine_cs *engine)
/* WaDisableGafsUnitClkGating:kbl */ /* WaDisableGafsUnitClkGating:kbl */
WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
/* WaDisableSbeCacheDispatchPortSharing:kbl */
WA_SET_BIT_MASKED(
GEN7_HALF_SLICE_CHICKEN1,
GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
/* WaDisableLSQCROPERFforOCL:kbl */ /* WaDisableLSQCROPERFforOCL:kbl */
ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
if (ret) if (ret)