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ixgbe: Add SR-IOV feature enablement code
Adds code to the core 82599 module to support SR-IOV features of the 82599 network controller Signed-off-by: Greg Rose <gregory.v.rose@intel.com> Acked-by: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -31,6 +31,7 @@
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#include "ixgbe.h"
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#include "ixgbe_phy.h"
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#include "ixgbe_mbx.h"
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#define IXGBE_82599_MAX_TX_QUEUES 128
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#define IXGBE_82599_MAX_RX_QUEUES 128
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@ -951,8 +952,6 @@ static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
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msleep(50);
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/*
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* Store the original AUTOC/AUTOC2 values if they have not been
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* stored off yet. Otherwise restore the stored original
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@ -1095,9 +1094,11 @@ static s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, u32 vind,
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bool vlan_on)
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{
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u32 regindex;
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u32 vlvf_index;
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u32 bitindex;
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u32 bits;
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u32 first_empty_slot;
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u32 vt_ctl;
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if (vlan > 4095)
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return IXGBE_ERR_PARAM;
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@ -1124,28 +1125,31 @@ static s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, u32 vind,
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/* Part 2
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* If the vind is set
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* If VT mode is set
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* Either vlan_on
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* make sure the vlan is in VLVF
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* set the vind bit in the matching VLVFB
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* Or !vlan_on
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* clear the pool bit and possibly the vind
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*/
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if (vind) {
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vt_ctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
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if (!(vt_ctl & IXGBE_VT_CTL_VT_ENABLE))
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goto out;
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/* find the vlanid or the first empty slot */
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first_empty_slot = 0;
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for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
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bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
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for (vlvf_index = 1; vlvf_index < IXGBE_VLVF_ENTRIES; vlvf_index++) {
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bits = IXGBE_READ_REG(hw, IXGBE_VLVF(vlvf_index));
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if (!bits && !first_empty_slot)
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first_empty_slot = regindex;
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first_empty_slot = vlvf_index;
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else if ((bits & 0x0FFF) == vlan)
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break;
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}
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if (regindex >= IXGBE_VLVF_ENTRIES) {
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if (vlvf_index >= IXGBE_VLVF_ENTRIES) {
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if (first_empty_slot)
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regindex = first_empty_slot;
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vlvf_index = first_empty_slot;
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else {
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hw_dbg(hw, "No space in VLVF.\n");
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goto out;
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@ -1156,44 +1160,49 @@ static s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, u32 vind,
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/* set the pool bit */
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if (vind < 32) {
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bits = IXGBE_READ_REG(hw,
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IXGBE_VLVFB(regindex * 2));
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IXGBE_VLVFB(vlvf_index * 2));
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bits |= (1 << vind);
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IXGBE_WRITE_REG(hw,
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IXGBE_VLVFB(regindex * 2), bits);
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IXGBE_VLVFB(vlvf_index * 2), bits);
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} else {
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bits = IXGBE_READ_REG(hw,
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IXGBE_VLVFB((regindex * 2) + 1));
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bits |= (1 << vind);
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IXGBE_VLVFB((vlvf_index * 2) + 1));
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bits |= (1 << (vind - 32));
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IXGBE_WRITE_REG(hw,
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IXGBE_VLVFB((regindex * 2) + 1), bits);
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IXGBE_VLVFB((vlvf_index * 2) + 1), bits);
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}
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} else {
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/* clear the pool bit */
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if (vind < 32) {
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bits = IXGBE_READ_REG(hw,
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IXGBE_VLVFB(regindex * 2));
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IXGBE_VLVFB(vlvf_index * 2));
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bits &= ~(1 << vind);
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IXGBE_WRITE_REG(hw,
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IXGBE_VLVFB(regindex * 2), bits);
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IXGBE_VLVFB(vlvf_index * 2), bits);
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bits |= IXGBE_READ_REG(hw,
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IXGBE_VLVFB((regindex * 2) + 1));
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IXGBE_VLVFB((vlvf_index * 2) + 1));
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} else {
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bits = IXGBE_READ_REG(hw,
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IXGBE_VLVFB((regindex * 2) + 1));
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bits &= ~(1 << vind);
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IXGBE_VLVFB((vlvf_index * 2) + 1));
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bits &= ~(1 << (vind - 32));
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IXGBE_WRITE_REG(hw,
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IXGBE_VLVFB((regindex * 2) + 1), bits);
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IXGBE_VLVFB((vlvf_index * 2) + 1), bits);
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bits |= IXGBE_READ_REG(hw,
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IXGBE_VLVFB(regindex * 2));
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IXGBE_VLVFB(vlvf_index * 2));
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}
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}
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if (bits)
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IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex),
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if (bits) {
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IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
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(IXGBE_VLVF_VIEN | vlan));
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else
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IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex), 0);
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/* if bits is non-zero then some pools/VFs are still
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* using this VLAN ID. Force the VFTA entry to on */
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bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
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bits |= (1 << bitindex);
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IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
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}
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else
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IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
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out:
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return 0;
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@ -2655,4 +2664,5 @@ struct ixgbe_info ixgbe_82599_info = {
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.mac_ops = &mac_ops_82599,
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.eeprom_ops = &eeprom_ops_82599,
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.phy_ops = &phy_ops_82599,
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.mbx_ops = &mbx_ops_82599,
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};
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