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drm/v3d: Set the correct DMA mask according to the MMU's limits.

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On 7278, we've got 40 bits to work with.

Signed-off-by: Eric Anholt <eric@anholt.net>
Link: https://patchwork.freedesktop.org/patch/msgid/20190419001014.23579-2-eric@anholt.net
Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
This commit is contained in:
Eric Anholt 2019-04-18 17:10:12 -07:00
parent 145986ec56
commit 091d628317
3 changed files with 14 additions and 1 deletions
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1
drivers/gpu/drm/v3d/v3d_debugfs.c
View File

@ -30,6 +30,7 @@ static const struct v3d_reg_def v3d_hub_reg_defs[] = {
REGDEF(V3D_MMU_CTL),
REGDEF(V3D_MMU_VIO_ADDR),
REGDEF(V3D_MMU_VIO_ID),
REGDEF(V3D_MMU_DEBUG_INFO),
};
static const struct v3d_reg_def v3d_gca_reg_defs[] = {

6
drivers/gpu/drm/v3d/v3d_drv.c
View File

@ -239,9 +239,9 @@ static int v3d_platform_drm_probe(struct platform_device *pdev)
struct drm_device *drm;
struct v3d_dev *v3d;
int ret;
u32 mmu_debug;
u32 ident1;
dev->coherent_dma_mask = DMA_BIT_MASK(36);
v3d = kzalloc(sizeof(*v3d), GFP_KERNEL);
if (!v3d)
@ -258,6 +258,10 @@ static int v3d_platform_drm_probe(struct platform_device *pdev)
if (ret)
goto dev_free;
mmu_debug = V3D_READ(V3D_MMU_DEBUG_INFO);
dev->coherent_dma_mask =
DMA_BIT_MASK(30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_PA_WIDTH));
ident1 = V3D_READ(V3D_HUB_IDENT1);
v3d->ver = (V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER) * 10 +
V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV));

8
drivers/gpu/drm/v3d/v3d_regs.h
View File

@ -191,6 +191,14 @@
/* Address that faulted */
#define V3D_MMU_VIO_ADDR 0x01234
#define V3D_MMU_DEBUG_INFO 0x01238
# define V3D_MMU_PA_WIDTH_MASK V3D_MASK(11, 8)
# define V3D_MMU_PA_WIDTH_SHIFT 8
# define V3D_MMU_VA_WIDTH_MASK V3D_MASK(7, 4)
# define V3D_MMU_VA_WIDTH_SHIFT 4
# define V3D_MMU_VERSION_MASK V3D_MASK(3, 0)
# define V3D_MMU_VERSION_SHIFT 0
/* Per-V3D-core registers */
#define V3D_CTL_IDENT0 0x00000