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ARM: dts: ARM: dts: Fix omap5 SDIO dat1 interrupt

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Few changes to fix issues I've noticed while debugging omap5-uevm
wl18xx issues:

1. Move wlcore irq pin muxing under wlcore. This irq could be
   different from gpio_wk14 on some board variants

2. Don't configure pull on wlcore irq pin. There is a 10k
   pull up resistor R105 on the device to VDDS_1v8_MAIN

3. The padconf register for wlsdio_data1 is wrong, it's really
   at 0x1a8 + 2 - 0x40 = 0x16a offset, not at 0x168 as that's
   for wlsdio_data0

4. Mark the omap5-uevm wlan as compatible with ti,wl1837 as
   that's what the TDK R078 part seems to be

5. The MMC interrupt for WLAN musb be wakeupgen, not gic

Looks like omap5-uevm WLAN behaves better now, but I still seem
to have issues with some access points.

Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Tony Lindgren 2016-09-11 21:01:02 -07:00
parent 84ae49747f
commit 08f9268b2a
2 changed files with 10 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
arch/arm/boot/dts/omap5-board-common.dtsi
View File

@ -332,7 +332,7 @@
wlcore_irq_pin: pinmux_wlcore_irq_pin {
pinctrl-single,pins = <
OMAP5_IOPAD(0x40, PIN_INPUT_PULLUP | MUX_MODE6) /* llia_wakereqin.gpio1_wk14 */
OMAP5_IOPAD(0x40, PIN_INPUT | MUX_MODE6) /* llia_wakereqin.gpio1_wk14 */
>;
};
};
@ -355,15 +355,17 @@
non-removable;
cap-power-off-card;
pinctrl-names = "default";
pinctrl-0 = <&mmc3_pins &wlcore_irq_pin>;
interrupts-extended = <&gic GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH
&omap5_pmx_core 0x168>;
pinctrl-0 = <&mmc3_pins>;
interrupts-extended = <&wakeupgen GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH
&omap5_pmx_core 0x16a>;
#address-cells = <1>;
#size-cells = <0>;
wlcore: wlcore@2 {
compatible = "ti,wl1271";
reg = <2>;
pinctrl-names = "default";
pinctrl-0 = <&wlcore_irq_pin>;
interrupt-parent = <&gpio1>;
interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; /* gpio 14 */
ref-clock-frequency = <26000000>;

4
arch/arm/boot/dts/omap5-uevm.dts
View File

@ -61,3 +61,7 @@
OMAP5_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */
>;
};
&wlcore {
compatible = "ti,wl1837";
};