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PCI: more fixes for PCIe Hotplug so that it works with ExpressCard slots on Dell notebooks (and others?) in conjunction with modparam of pciehp_force=1
Split out the hotplug hardware initialization code from pcie_init() into pcie_init_enable_events(), without changing any functionality. Signed-off-by: Mark Lord <mlord@pobox.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Theodore Ts'o <tytso@mit.edu> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Mark Lord
Greg Kroah-Hartman
parent
0a3c33d77f
commit
08e7a7d27d
@ -1067,99 +1067,22 @@ int pciehp_acpi_get_hp_hw_control_from_firmware(struct pci_dev *dev)
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}
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#endif
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int pcie_init(struct controller * ctrl, struct pcie_device *dev)
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int pcie_init_hardware(struct controller *ctrl, struct pcie_device *dev)
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{
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int rc;
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u16 temp_word;
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u16 cap_reg;
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u16 intr_enable = 0;
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u32 slot_cap;
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int cap_base;
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u16 slot_status, slot_ctrl;
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u16 slot_status;
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struct pci_dev *pdev;
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pdev = dev->port;
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ctrl->pci_dev = pdev; /* save pci_dev in context */
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dbg("%s: hotplug controller vendor id 0x%x device id 0x%x\n",
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__FUNCTION__, pdev->vendor, pdev->device);
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if ((cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP)) == 0) {
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dbg("%s: Can't find PCI_CAP_ID_EXP (0x10)\n", __FUNCTION__);
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goto abort_free_ctlr;
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}
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ctrl->cap_base = cap_base;
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dbg("%s: pcie_cap_base %x\n", __FUNCTION__, cap_base);
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rc = pciehp_readw(ctrl, CAPREG, &cap_reg);
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if (rc) {
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err("%s: Cannot read CAPREG register\n", __FUNCTION__);
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goto abort_free_ctlr;
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}
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dbg("%s: CAPREG offset %x cap_reg %x\n",
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__FUNCTION__, ctrl->cap_base + CAPREG, cap_reg);
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if (((cap_reg & SLOT_IMPL) == 0) ||
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(((cap_reg & DEV_PORT_TYPE) != 0x0040)
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&& ((cap_reg & DEV_PORT_TYPE) != 0x0060))) {
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dbg("%s : This is not a root port or the port is not "
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"connected to a slot\n", __FUNCTION__);
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goto abort_free_ctlr;
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}
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rc = pciehp_readl(ctrl, SLOTCAP, &slot_cap);
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if (rc) {
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err("%s: Cannot read SLOTCAP register\n", __FUNCTION__);
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goto abort_free_ctlr;
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}
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dbg("%s: SLOTCAP offset %x slot_cap %x\n",
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__FUNCTION__, ctrl->cap_base + SLOTCAP, slot_cap);
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if (!(slot_cap & HP_CAP)) {
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dbg("%s : This slot is not hot-plug capable\n", __FUNCTION__);
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goto abort_free_ctlr;
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}
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/* For debugging purpose */
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rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
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if (rc) {
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err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
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goto abort_free_ctlr;
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}
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dbg("%s: SLOTSTATUS offset %x slot_status %x\n",
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__FUNCTION__, ctrl->cap_base + SLOTSTATUS, slot_status);
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rc = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
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if (rc) {
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err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
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goto abort_free_ctlr;
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}
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dbg("%s: SLOTCTRL offset %x slot_ctrl %x\n",
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__FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
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for (rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++)
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if (pci_resource_len(pdev, rc) > 0)
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dbg("pci resource[%d] start=0x%llx(len=0x%llx)\n", rc,
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(unsigned long long)pci_resource_start(pdev, rc),
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(unsigned long long)pci_resource_len(pdev, rc));
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info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
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pdev->vendor, pdev->device,
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pdev->subsystem_vendor, pdev->subsystem_device);
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mutex_init(&ctrl->crit_sect);
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mutex_init(&ctrl->ctrl_lock);
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spin_lock_init(&ctrl->lock);
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/* setup wait queue */
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init_waitqueue_head(&ctrl->queue);
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/* return PCI Controller Info */
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ctrl->slot_device_offset = 0;
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ctrl->num_slots = 1;
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ctrl->first_slot = slot_cap >> 19;
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ctrl->ctrlcap = slot_cap & 0x0000007f;
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/* Mask Hot-plug Interrupt Enable */
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rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
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@ -1280,8 +1203,6 @@ int pcie_init(struct controller * ctrl, struct pcie_device *dev)
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goto abort_disable_intr;
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}
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ctrl->hpc_ops = &pciehp_hpc_ops;
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return 0;
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/* We end up here for the many possible ways to fail this API. */
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@ -1303,3 +1224,105 @@ abort_free_irq:
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abort_free_ctlr:
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return -1;
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}
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int pcie_init(struct controller *ctrl, struct pcie_device *dev)
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{
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int rc;
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u16 cap_reg;
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u32 slot_cap;
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int cap_base;
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u16 slot_status, slot_ctrl;
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struct pci_dev *pdev;
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pdev = dev->port;
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ctrl->pci_dev = pdev; /* save pci_dev in context */
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dbg("%s: hotplug controller vendor id 0x%x device id 0x%x\n",
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__FUNCTION__, pdev->vendor, pdev->device);
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cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP);
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if (cap_base == 0) {
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dbg("%s: Can't find PCI_CAP_ID_EXP (0x10)\n", __FUNCTION__);
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goto abort;
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}
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ctrl->cap_base = cap_base;
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dbg("%s: pcie_cap_base %x\n", __FUNCTION__, cap_base);
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rc = pciehp_readw(ctrl, CAPREG, &cap_reg);
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if (rc) {
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err("%s: Cannot read CAPREG register\n", __FUNCTION__);
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goto abort;
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}
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dbg("%s: CAPREG offset %x cap_reg %x\n",
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__FUNCTION__, ctrl->cap_base + CAPREG, cap_reg);
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if (((cap_reg & SLOT_IMPL) == 0) ||
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(((cap_reg & DEV_PORT_TYPE) != 0x0040)
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&& ((cap_reg & DEV_PORT_TYPE) != 0x0060))) {
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dbg("%s : This is not a root port or the port is not "
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"connected to a slot\n", __FUNCTION__);
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goto abort;
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}
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rc = pciehp_readl(ctrl, SLOTCAP, &slot_cap);
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if (rc) {
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err("%s: Cannot read SLOTCAP register\n", __FUNCTION__);
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goto abort;
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}
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dbg("%s: SLOTCAP offset %x slot_cap %x\n",
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__FUNCTION__, ctrl->cap_base + SLOTCAP, slot_cap);
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if (!(slot_cap & HP_CAP)) {
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dbg("%s : This slot is not hot-plug capable\n", __FUNCTION__);
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goto abort;
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}
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/* For debugging purpose */
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rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
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if (rc) {
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err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
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goto abort;
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}
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dbg("%s: SLOTSTATUS offset %x slot_status %x\n",
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__FUNCTION__, ctrl->cap_base + SLOTSTATUS, slot_status);
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rc = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
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if (rc) {
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err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
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goto abort;
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}
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dbg("%s: SLOTCTRL offset %x slot_ctrl %x\n",
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__FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
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for (rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++)
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if (pci_resource_len(pdev, rc) > 0)
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dbg("pci resource[%d] start=0x%llx(len=0x%llx)\n", rc,
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(unsigned long long)pci_resource_start(pdev, rc),
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(unsigned long long)pci_resource_len(pdev, rc));
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info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
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pdev->vendor, pdev->device,
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pdev->subsystem_vendor, pdev->subsystem_device);
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mutex_init(&ctrl->crit_sect);
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mutex_init(&ctrl->ctrl_lock);
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spin_lock_init(&ctrl->lock);
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/* setup wait queue */
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init_waitqueue_head(&ctrl->queue);
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/* return PCI Controller Info */
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ctrl->slot_device_offset = 0;
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ctrl->num_slots = 1;
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ctrl->first_slot = slot_cap >> 19;
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ctrl->ctrlcap = slot_cap & 0x0000007f;
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rc = pcie_init_hardware(ctrl, dev);
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if (rc == 0) {
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ctrl->hpc_ops = &pciehp_hpc_ops;
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return 0;
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}
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abort:
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return -1;
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}
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