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mtd: nand: lpc32xx_slc: fix potential overflow over 4 bits
In case if quotient of controller clock rate to device clock rate does not fit into 4 bit value, choose the maximum acceptable value 0xF, which stands for 16 clocks. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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* slc_tac register definitions
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**********************************************************************/
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/* Computation of clock cycles on basis of controller and device clock rates */
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#define SLCTAC_CLOCKS(c, n, s) (((1 + (c / n)) & 0xF) << s)
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#define SLCTAC_CLOCKS(c, n, s) (min_t(u32, 1 + (c / n), 0xF) << s)
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/* Clock setting for RDY write sample wait time in 2*n clocks */
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#define SLCTAC_WDR(n) (((n) & 0xF) << 28)
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