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gpio-stp-xway: Fix enabling the highest bit of the PHY LEDs

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0x3 only masks two bits, but three bits have to be allowed. This fixes
GPHY0 LED2 (which is the highest bit of phy2) on my board.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Martin Blumenstingl 2015-05-25 22:39:50 +02:00 committed by Linus Walleij
parent b6ac1280b6
commit 08b085a07e
1 changed files with 1 additions and 1 deletions
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2
drivers/gpio/gpio-stp-xway.c
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@ -58,7 +58,7 @@
#define XWAY_STP_ADSL_MASK 0x3
/* 2 groups of 3 bits can be driven by the phys */
#define XWAY_STP_PHY_MASK 0x3
#define XWAY_STP_PHY_MASK 0x7
#define XWAY_STP_PHY1_SHIFT 27
#define XWAY_STP_PHY2_SHIFT 15