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drm/tegra: dc: Move more code into ->init()
The code in tegra_crtc_prepare() really belongs in tegra_dc_init(), or at least most of it. This fixes an issue with VBLANK handling because tegra_crtc_prepare() would overwrite the interrupt mask register that tegra_crtc_enable_vblank() had written to to enable VBLANK interrupts. Tested-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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07d05cbf60
@ -1230,9 +1230,6 @@ static void tegra_crtc_mode_set_nofb(struct drm_crtc *crtc)
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/* program display mode */
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tegra_dc_set_timings(dc, mode);
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if (dc->soc->supports_border_color)
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tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
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/* interlacing isn't supported yet, so disable it */
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if (dc->soc->supports_interlacing) {
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value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
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@ -1255,42 +1252,7 @@ static void tegra_crtc_mode_set_nofb(struct drm_crtc *crtc)
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static void tegra_crtc_prepare(struct drm_crtc *crtc)
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{
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struct tegra_dc *dc = to_tegra_dc(crtc);
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unsigned int syncpt;
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unsigned long value;
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drm_crtc_vblank_off(crtc);
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if (dc->pipe)
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syncpt = SYNCPT_VBLANK1;
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else
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syncpt = SYNCPT_VBLANK0;
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/* initialize display controller */
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tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
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tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC);
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value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT;
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tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
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value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
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WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
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tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
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/* initialize timer */
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value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
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WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
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tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
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value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
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WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
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tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
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value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
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tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
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value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
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tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
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}
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static void tegra_crtc_commit(struct drm_crtc *crtc)
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@ -1667,6 +1629,8 @@ static int tegra_dc_init(struct host1x_client *client)
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struct tegra_drm *tegra = drm->dev_private;
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struct drm_plane *primary = NULL;
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struct drm_plane *cursor = NULL;
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unsigned int syncpt;
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u32 value;
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int err;
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if (tegra->domain) {
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@ -1733,6 +1697,40 @@ static int tegra_dc_init(struct host1x_client *client)
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goto cleanup;
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}
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/* initialize display controller */
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if (dc->pipe)
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syncpt = SYNCPT_VBLANK1;
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else
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syncpt = SYNCPT_VBLANK0;
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tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
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tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC);
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value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT;
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tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
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value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
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WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
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tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
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/* initialize timer */
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value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
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WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
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tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
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value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
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WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
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tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
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value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
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tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
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value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
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tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
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if (dc->soc->supports_border_color)
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tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
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return 0;
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cleanup:
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