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Samsung fixes-2 for v3.16

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- fix the check for SMP configuration with using CONFIG_SMP
   not just SMP
 - fix the number of pwm-cells for exynos4 pwm
 - fix ftrace for exynos_mct
 - register exynos_mct for stable udely
 - fix secondary boot addr for secure mode for exynos SoCs
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Merge tag 'samsung-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into fixes

Merge "Samsung fixes-2 for v3.16" from Kukjin Kim:

- fix the check for SMP configuration with using CONFIG_SMP
  not just SMP
- fix the number of pwm-cells for exynos4 pwm
- fix ftrace for exynos_mct
- register exynos_mct for stable udely
- fix secondary boot addr for secure mode for exynos SoCs

* tag 'samsung-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  ARM: EXYNOS: Update secondary boot addr for secure mode
  clocksource: exynos_mct: Register the timer for stable udelay
  clocksource: exynos_mct: Fix ftrace
  ARM: dts: fix pwm-cells in pwm node for exynos4
  ARM: EXYNOS: Fix the check for non-smp configuration

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2014-07-07 21:10:17 -07:00
commit 069c70cb07
4 changed files with 27 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/boot/dts/exynos4.dtsi
View File

@ -554,7 +554,7 @@
interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>;
clocks = <&clock CLK_PWM>;
clock-names = "timers";
#pwm-cells = <2>;
#pwm-cells = <3>;
status = "disabled";
};

2
arch/arm/mach-exynos/exynos.c
View File

@ -297,7 +297,7 @@ static void __init exynos_dt_machine_init(void)
* This is called from smp_prepare_cpus if we've built for SMP, but
* we still need to set it up for PM and firmware ops if not.
*/
if (!IS_ENABLED(SMP))
if (!IS_ENABLED(CONFIG_SMP))
exynos_sysram_init();
exynos_cpuidle_init();

7
arch/arm/mach-exynos/firmware.c
View File

@ -57,7 +57,12 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
boot_reg = sysram_ns_base_addr + 0x1c;
if (!soc_is_exynos4212() && !soc_is_exynos3250())
/*
* Almost all Exynos-series of SoCs that run in secure mode don't need
* additional offset for every CPU, with Exynos4412 being the only
* exception.
*/
if (soc_is_exynos4412())
boot_reg += 4 * cpu;
__raw_writel(boot_addr, boot_reg);

20
drivers/clocksource/exynos_mct.c
View File

@ -162,7 +162,7 @@ static void exynos4_mct_frc_start(void)
exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
}
static cycle_t exynos4_frc_read(struct clocksource *cs)
static cycle_t notrace _exynos4_frc_read(void)
{
unsigned int lo, hi;
u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
@ -176,6 +176,11 @@ static cycle_t exynos4_frc_read(struct clocksource *cs)
return ((cycle_t)hi << 32) | lo;
}
static cycle_t exynos4_frc_read(struct clocksource *cs)
{
return _exynos4_frc_read();
}
static void exynos4_frc_resume(struct clocksource *cs)
{
exynos4_mct_frc_start();
@ -192,13 +197,24 @@ struct clocksource mct_frc = {
static u64 notrace exynos4_read_sched_clock(void)
{
return exynos4_frc_read(&mct_frc);
return _exynos4_frc_read();
}
static struct delay_timer exynos4_delay_timer;
static cycles_t exynos4_read_current_timer(void)
{
return _exynos4_frc_read();
}
static void __init exynos4_clocksource_init(void)
{
exynos4_mct_frc_start();
exynos4_delay_timer.read_current_timer = &exynos4_read_current_timer;
exynos4_delay_timer.freq = clk_rate;
register_current_timer_delay(&exynos4_delay_timer);
if (clocksource_register_hz(&mct_frc, clk_rate))
panic("%s: can't register clocksource\n", mct_frc.name);