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Samsung fixes-2 for v3.16
- fix the check for SMP configuration with using CONFIG_SMP not just SMP - fix the number of pwm-cells for exynos4 pwm - fix ftrace for exynos_mct - register exynos_mct for stable udely - fix secondary boot addr for secure mode for exynos SoCs -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJTuyiZAAoJEA0Cl+kVi2xqDCQQAI59MYn7mOSxQ4egjR65SFXc 5g0yQIGsfWw1+FXDr1X64Okq5HjY8YHTbkyo9nzjNcmABwHK/oJXWVpJuk4b61e6 eKA5hgiSa1grvz4uzW1ZR+pRooEOn7sJe3OYcesPrsbnsXBLzmV+9HJ2x657asCx Ran010mw+QNfyOikARFIWaVB9REbK1n5mcKAoAeW3iFAp94xCH0d5Qj0IiQxAam9 8zdEogfY3+YcB+frOaZH1OzVCZ1wLjDdmv86SwvcixuvPU7Lcr91vDFbc0cE7DVj pHZtIoMi8RZk3twtMLhAnJz+fNygUGN7kBMW3P42ULkgMxIQMGfqmWvgBpUJ8XO6 2wVZ6WnW6jN1OXyNsNM/yyDtm+hdryaIP+WdMfrol8gRevilNniyPwd83HSKTJg8 HHAazUAZZTS+04x19aBBO2RU5vhHSimbOOsXIlJen4Tz5BBwebDQ38JnKRSElgm1 5w+8BajzVt5YTaW2NJ7T87wb/ytV8/MNKZ58GOzh2EXIbnohKbs0qM1ip0RztWLA ZvEyTF86+fA55W5wrSb6qfz428hCWkJ1PnPCXVPvffNGsrdOM+ziC8G1fhDVw5TJ TVoktLhz7kU+1aB7272NbXVI9GaJ8vTl0pMpcN5sHI4NCq3g+8SylfaJt3aW5zcy kKsxM4bvZyMXstwAIlVo =jlRt -----END PGP SIGNATURE----- Merge tag 'samsung-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into fixes Merge "Samsung fixes-2 for v3.16" from Kukjin Kim: - fix the check for SMP configuration with using CONFIG_SMP not just SMP - fix the number of pwm-cells for exynos4 pwm - fix ftrace for exynos_mct - register exynos_mct for stable udely - fix secondary boot addr for secure mode for exynos SoCs * tag 'samsung-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: EXYNOS: Update secondary boot addr for secure mode clocksource: exynos_mct: Register the timer for stable udelay clocksource: exynos_mct: Fix ftrace ARM: dts: fix pwm-cells in pwm node for exynos4 ARM: EXYNOS: Fix the check for non-smp configuration Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
commit
069c70cb07
@ -554,7 +554,7 @@
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interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>;
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clocks = <&clock CLK_PWM>;
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clock-names = "timers";
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#pwm-cells = <2>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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@ -297,7 +297,7 @@ static void __init exynos_dt_machine_init(void)
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* This is called from smp_prepare_cpus if we've built for SMP, but
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* we still need to set it up for PM and firmware ops if not.
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*/
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if (!IS_ENABLED(SMP))
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if (!IS_ENABLED(CONFIG_SMP))
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exynos_sysram_init();
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exynos_cpuidle_init();
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@ -57,8 +57,13 @@ static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
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boot_reg = sysram_ns_base_addr + 0x1c;
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if (!soc_is_exynos4212() && !soc_is_exynos3250())
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boot_reg += 4*cpu;
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/*
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* Almost all Exynos-series of SoCs that run in secure mode don't need
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* additional offset for every CPU, with Exynos4412 being the only
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* exception.
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*/
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if (soc_is_exynos4412())
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boot_reg += 4 * cpu;
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__raw_writel(boot_addr, boot_reg);
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return 0;
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@ -162,7 +162,7 @@ static void exynos4_mct_frc_start(void)
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exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
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}
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static cycle_t exynos4_frc_read(struct clocksource *cs)
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static cycle_t notrace _exynos4_frc_read(void)
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{
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unsigned int lo, hi;
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u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
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@ -176,6 +176,11 @@ static cycle_t exynos4_frc_read(struct clocksource *cs)
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return ((cycle_t)hi << 32) | lo;
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}
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static cycle_t exynos4_frc_read(struct clocksource *cs)
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{
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return _exynos4_frc_read();
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}
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static void exynos4_frc_resume(struct clocksource *cs)
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{
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exynos4_mct_frc_start();
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@ -192,13 +197,24 @@ struct clocksource mct_frc = {
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static u64 notrace exynos4_read_sched_clock(void)
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{
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return exynos4_frc_read(&mct_frc);
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return _exynos4_frc_read();
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}
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static struct delay_timer exynos4_delay_timer;
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static cycles_t exynos4_read_current_timer(void)
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{
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return _exynos4_frc_read();
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}
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static void __init exynos4_clocksource_init(void)
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{
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exynos4_mct_frc_start();
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exynos4_delay_timer.read_current_timer = &exynos4_read_current_timer;
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exynos4_delay_timer.freq = clk_rate;
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register_current_timer_delay(&exynos4_delay_timer);
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if (clocksource_register_hz(&mct_frc, clk_rate))
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panic("%s: can't register clocksource\n", mct_frc.name);
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