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x86/MCE: Determine MCA banks' init state properly
The OS is expected to write all bits to MCA_CTL for each bank, thus enabling error reporting in all banks. However, some banks may be unused in which case the registers for such banks are Read-as-Zero/Writes-Ignored. Also, the OS may avoid setting some control bits because of quirks, etc. A bank can be considered uninitialized if the MCA_CTL register returns zero. This is because either the OS did not write anything or because the hardware is enforcing RAZ/WI for the bank. Set a bank's init value based on if the control bits are set or not in hardware. Return an error code in the sysfs interface for uninitialized banks. Do a final bank init check in a separate function which is not part of any user-controlled code flows. This is so a user may enable/disable a bank during runtime without having to restart their system. [ bp: Massage a bit. Discover bank init state at boot. ] Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> Signed-off-by: Borislav Petkov <bp@suse.de> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: "linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Tony Luck <tony.luck@intel.com> Cc: "x86@kernel.org" <x86@kernel.org> Link: https://lkml.kernel.org/r/20190607201752.221446-6-Yazen.Ghannam@amd.com
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@ -1490,6 +1490,11 @@ static void __mcheck_cpu_mce_banks_init(void)
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for (i = 0; i < n_banks; i++) {
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struct mce_bank *b = &mce_banks[i];
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/*
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* Init them all, __mcheck_cpu_apply_quirks() is going to apply
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* the required vendor quirks before
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* __mcheck_cpu_init_clear_banks() does the final bank setup.
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*/
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b->ctl = -1ULL;
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b->init = 1;
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}
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@ -1562,6 +1567,33 @@ static void __mcheck_cpu_init_clear_banks(void)
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}
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}
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/*
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* Do a final check to see if there are any unused/RAZ banks.
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*
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* This must be done after the banks have been initialized and any quirks have
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* been applied.
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*
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* Do not call this from any user-initiated flows, e.g. CPU hotplug or sysfs.
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* Otherwise, a user who disables a bank will not be able to re-enable it
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* without a system reboot.
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*/
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static void __mcheck_cpu_check_banks(void)
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{
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struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
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u64 msrval;
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int i;
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for (i = 0; i < this_cpu_read(mce_num_banks); i++) {
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struct mce_bank *b = &mce_banks[i];
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if (!b->init)
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continue;
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rdmsrl(msr_ops.ctl(i), msrval);
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b->init = !!msrval;
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}
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}
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/*
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* During IFU recovery Sandy Bridge -EP4S processors set the RIPV and
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* EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM
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@ -1849,6 +1881,7 @@ void mcheck_cpu_init(struct cpuinfo_x86 *c)
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__mcheck_cpu_init_generic();
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__mcheck_cpu_init_vendor(c);
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__mcheck_cpu_init_clear_banks();
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__mcheck_cpu_check_banks();
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__mcheck_cpu_setup_timer();
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}
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@ -2085,6 +2118,9 @@ static ssize_t show_bank(struct device *s, struct device_attribute *attr,
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b = &per_cpu(mce_banks_array, s->id)[bank];
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if (!b->init)
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return -ENODEV;
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return sprintf(buf, "%llx\n", b->ctl);
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}
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@ -2103,6 +2139,9 @@ static ssize_t set_bank(struct device *s, struct device_attribute *attr,
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b = &per_cpu(mce_banks_array, s->id)[bank];
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if (!b->init)
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return -ENODEV;
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b->ctl = new;
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mce_restart();
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