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ARM: S5P6442: Add DMA operation clock
This patch adds DMA operation clock which is disabled as default. Signed-off-by: Seungwhan Youn <sw.youn@samsung.com> Acked-by: Jassi Brar <jassi.brar@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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8e0e9e2958
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06185c0762
@ -192,6 +192,11 @@ static struct clk clk_pclkd1 = {
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.parent = &clk_hclkd1,
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};
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int s5p6442_clk_ip0_ctrl(struct clk *clk, int enable)
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{
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return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
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}
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int s5p6442_clk_ip3_ctrl(struct clk *clk, int enable)
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{
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return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
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@ -335,6 +340,16 @@ void __init_or_cpufreq s5p6442_setup_clocks(void)
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clk_pclkd1.rate = pclkd1;
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}
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static struct clk init_clocks_disable[] = {
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{
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.name = "pdma",
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.id = -1,
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.parent = &clk_pclkd1,
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.enable = s5p6442_clk_ip0_ctrl,
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.ctrlbit = (1 << 3),
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},
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};
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static struct clk init_clocks[] = {
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{
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.name = "systimer",
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@ -393,10 +408,23 @@ static struct clk *clks[] __initdata = {
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void __init s5p6442_register_clocks(void)
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{
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struct clk *clkptr;
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int i, ret;
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s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
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s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
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s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
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clkptr = init_clocks_disable;
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for (i = 0; i < ARRAY_SIZE(init_clocks_disable); i++, clkptr++) {
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ret = s3c24xx_register_clock(clkptr);
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if (ret < 0) {
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printk(KERN_ERR "Fail to register clock %s (%d)\n",
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clkptr->name, ret);
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} else
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(clkptr->enable)(clkptr, 0);
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}
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s3c_pwmclk_init();
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}
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@ -46,6 +46,7 @@
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#define S5P_CLK_DIV5 S5P_CLKREG(0x314)
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#define S5P_CLK_DIV6 S5P_CLKREG(0x318)
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#define S5P_CLKGATE_IP0 S5P_CLKREG(0x460)
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#define S5P_CLKGATE_IP3 S5P_CLKREG(0x46C)
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/* CLK_OUT */
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