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mmc: sdhci-of-esdhc: set the sd clock divisor value above 3
This patch is to set the sd clock divisor value above 3 in tuning mode Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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@ -830,9 +830,17 @@ static int esdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
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bool hs400_tuning;
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unsigned int clk;
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u32 val;
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int ret;
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/* For tuning mode, the sd clock divisor value
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* must be larger than 3 according to reference manual.
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*/
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clk = esdhc->peripheral_clock / 3;
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if (host->clock > clk)
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esdhc_of_set_clock(host, clk);
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if (esdhc->quirk_limited_clk_division &&
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host->flags & SDHCI_HS400_TUNING)
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esdhc_of_set_clock(host, host->clock);
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