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arm64: cpufeature: Track 32bit EL0 support
Add cpu_hwcap bit for keeping track of the support for 32bit EL0. Tested-by: Yury Norov <ynorov@caviumnetworks.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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@ -35,8 +35,9 @@
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#define ARM64_ALT_PAN_NOT_UAO 10
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#define ARM64_HAS_VIRT_HOST_EXTN 11
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#define ARM64_WORKAROUND_CAVIUM_27456 12
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#define ARM64_HAS_32BIT_EL0 13
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#define ARM64_NCAPS 13
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#define ARM64_NCAPS 14
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#ifndef __ASSEMBLY__
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@ -192,6 +193,11 @@ static inline bool cpu_supports_mixed_endian_el0(void)
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return id_aa64mmfr0_mixed_endian_el0(read_cpuid(ID_AA64MMFR0_EL1));
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}
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static inline bool system_supports_32bit_el0(void)
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{
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return cpus_have_cap(ARM64_HAS_32BIT_EL0);
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}
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static inline bool system_supports_mixed_endian_el0(void)
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{
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return id_aa64mmfr0_mixed_endian_el0(read_system_reg(SYS_ID_AA64MMFR0_EL1));
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@ -737,6 +737,15 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
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.capability = ARM64_HAS_VIRT_HOST_EXTN,
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.matches = runs_at_el2,
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},
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{
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.desc = "32-bit EL0 Support",
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.capability = ARM64_HAS_32BIT_EL0,
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.matches = has_cpuid_feature,
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.sys_reg = SYS_ID_AA64PFR0_EL1,
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.sign = FTR_UNSIGNED,
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.field_pos = ID_AA64PFR0_EL0_SHIFT,
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.min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
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},
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{},
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};
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